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yosys.git
2019-04-16
Eddie Hung
Do not call abc on modules with abc_box_id attr
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2019-04-16
Eddie Hung
Revert "Add abc_box_id attribute to MUXF7/F8 cells"
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2019-04-16
Eddie Hung
Use abc_box_id
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2019-04-16
Eddie Hung
Check abc_box_id attr
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2019-04-16
Eddie Hung
Add abc_box_id attribute to MUXF7/F8 cells
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2019-04-16
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-16
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-16
Eddie Hung
Merge pull request #937 from YosysHQ/revert-932-eddie...
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2019-04-16
Eddie Hung
Revert "Recognise default entry in case even if all...
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2019-04-15
Eddie Hung
Merge pull request #936 from YosysHQ/README-fix-quotes
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2019-04-15
whitequark
README: fix some incorrect quoting.
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2019-04-13
Eddie Hung
Forgot backslashes
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2019-04-13
Eddie Hung
Handle __dummy_o__ and __const[01]__ in read_aiger...
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2019-04-13
Eddie Hung
abc to ignore __dummy_o__ and __const[01]__ when re...
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2019-04-13
Eddie Hung
Output __const0__ and __const1__ CIs
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2019-04-13
Eddie Hung
Merge branch 'xaig' of github.com:YosysHQ/yosys into...
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2019-04-13
Eddie Hung
Fix inout handling for -map option
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2019-04-12
Eddie Hung
Merge branch 'xaig' of github.com:YosysHQ/yosys into...
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12
Eddie Hung
Use -map instead of -symbols for aiger
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2019-04-12
Eddie Hung
ci_bits and co_bits now a list, order is important...
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2019-04-12
Eddie Hung
Also cope with duplicated CIs
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2019-04-12
Eddie Hung
WIP
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2019-04-12
Eddie Hung
Comment out
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2019-04-12
Eddie Hung
Add support for synth_xilinx -abc9 and ignore abc9...
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2019-04-12
Eddie Hung
Cope with an output having same name as an input (i...
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12
Eddie Hung
Merge pull request #928 from litghost/add_xc7_sim_models
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2019-04-12
Eddie Hung
PI before CI
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-04-12
Keith Rothman
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
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2019-04-12
Clifford Wolf
Merge pull request #933 from dh73/master
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2019-04-12
Clifford Wolf
Merge pull request #932 from YosysHQ/eddie/fixdlatch
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2019-04-12
Diego
Fixing issues in CycloneV cell sim
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2019-04-11
Eddie Hung
Merge remote-tracking branch 'origin/pmux2shiftx' into...
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2019-04-11
Eddie Hung
More unused
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2019-04-11
Eddie Hung
Merge remote-tracking branch 'origin/pmux2shiftx' into...
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2019-04-11
Eddie Hung
Remove unused
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2019-04-11
Eddie Hung
Fixes
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2019-04-11
Eddie Hung
WIP
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2019-04-11
Eddie Hung
Spelling fixes
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2019-04-11
Eddie Hung
Add default entry to testcase
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2019-04-11
Eddie Hung
Recognise default entry in case even if all cases cover...
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2019-04-11
Eddie Hung
Fix cells_map.v some more
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2019-04-11
Eddie Hung
More fine tuning
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2019-04-11
Eddie Hung
Fix cells_map.v
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2019-04-11
Eddie Hung
Fix typo
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2019-04-11
Eddie Hung
Juggle opt calls in synth_xilinx
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2019-04-11
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-11
Eddie Hung
Add non-input bits driven by unrecognised cells as...
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2019-04-11
Eddie Hung
WIP for cells_map.v -- maybe working?
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2019-04-10
Eddie Hung
Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1
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2019-04-10
Eddie Hung
Fix for when B_SIGNED = 1
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2019-04-10
Eddie Hung
Update doc for synth_xilinx
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2019-04-10
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-10
Eddie Hung
parse_aiger() to rename all $lut cells after "clean"
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2019-04-10
Eddie Hung
ff_map.v after abc
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2019-04-10
Eddie Hung
Tidy up
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2019-04-10
Eddie Hung
Move map_cells to before map_luts
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2019-04-10
Eddie Hung
WIP for $shiftx to wide mux
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2019-04-10
Eddie Hung
Update LUT delays
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2019-04-09
Eddie Hung
Add cells.lut to techlibs/xilinx/
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2019-04-09
Eddie Hung
synth_xilinx to call abc with -lut +/xilinx/cells.lut
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2019-04-09
Eddie Hung
Add delays to cells.box
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2019-04-09
Eddie Hung
Add "-lut <file>" support to abc9
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2019-04-09
Keith Rothman
Fix LUT6_2 definition.
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2019-04-09
Eddie Hung
synth_xilinx with abc9 to use -box
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2019-04-09
Eddie Hung
Add techlibs/xilinx/cells.box
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2019-04-09
Eddie Hung
Add "-box" option to abc9
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2019-04-09
Eddie Hung
Add 'setundef -zero' call prior to aigmap in abc9
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2019-04-09
Eddie Hung
Comment out
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2019-04-09
Eddie Hung
Add support for synth_xilinx -abc9 and ignore abc9...
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2019-04-09
Keith Rothman
Add additional cells sim models for core 7-series prima...
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2019-04-08
Eddie Hung
Fix a few typos
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2019-04-08
Eddie Hung
More space fixing
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2019-04-08
Eddie Hung
Fix spacing
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2019-04-08
Eddie Hung
Merge branch 'master' into xaig
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2019-04-08
Clifford Wolf
Merge pull request #919 from YosysHQ/multiport_transp
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2019-04-07
David Shah
memory_bram: Fix multiport make_transp
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2019-04-05
Clifford Wolf
Add "read_ilang -lib"
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2019-04-04
Clifford Wolf
Added missing argument checking to "mutate" command
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2019-04-03
Eddie Hung
Merge pull request #913 from smunaut/fix_proc_mux
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2019-04-03
Sylvain Munaut
proc_mux: Fix crash when trying to optimize non-existan...
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2019-04-03
Clifford Wolf
Merge pull request #912 from YosysHQ/bram_addr_en
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2019-04-03
Clifford Wolf
Merge pull request #910 from ucb-bar/memupdates
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2019-04-02
David Shah
memory_bram: Consider read enable for address expansion...
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2019-04-02
Eddie Hung
Merge pull request #895 from YosysHQ/pmux2shiftx
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2019-04-01
Jim Lawson
Refine memory support to deal with general Verilog...
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2019-03-29
Clifford Wolf
Merge pull request #907 from YosysHQ/clifford/fix906
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2019-03-29
Clifford Wolf
Build Verilog parser with -DYYMAXDEPTH=100000, fixes...
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2019-03-28
Clifford Wolf
Merge pull request #901 from trcwm/libertyfixes
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2019-03-28
Clifford Wolf
Merge pull request #903 from YosysHQ/bram_reset_transp
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2019-03-27
David Shah
memory_bram: Reset make_transp when growing read ports
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2019-03-27
Niels Moseley
Liberty file parser now accepts superfluous ;
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2019-03-27
Niels Moseley
Liberty file parser now accepts superfluous ;
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2019-03-27
Niels Moseley
Liberty file parser now accepts superfluous ;
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2019-03-27
Clifford Wolf
Add "read -verific" and "read -noverific"
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2019-03-27
Clifford Wolf
Add "rename -output"
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2019-03-27
Clifford Wolf
Improve "rename" help message
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2019-03-26
Clifford Wolf
Add "cutpoint -undef"
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