libresoc-litex.git
2021-09-19 Las SafinAdd more supported GCC triples
2021-06-10 Luke Kenneth... whoops spimaster (mspi0) not connected up
2021-06-09 Luke Kenneth... doh, supposed to subtract 16 not throw the calculation...
2021-06-09 Luke Kenneth... sort out PLL connection, in and out of peripheral inter...
2021-06-09 Luke Kenneth... try setting domain to "CPU"
2021-06-09 Luke Kenneth... try setting actual clk to pllclk_o
2021-06-09 Luke Kenneth... add PLL clock loop-back into CPU
2021-06-09 Luke Kenneth... add PLL clock loop-back into CPU
2021-06-09 Luke Kenneth... remove 16 NC, added 16 VCC/VDD
2021-06-03 Luke Kenneth... syntax error in pll.v
2021-06-03 Luke Kenneth... dummy PLL added with bypass, rename ref to ref_v due...
2021-05-26 Luke Kenneth... remove wb err signal from sram4k
2021-05-25 Luke Kenneth... increase not-connected pins in ls180
2021-05-22 Luke Kenneth... match up PLL names
2021-05-22 Luke Kenneth... match up PLL names
2021-05-22 Luke Kenneth... rename vco_test_ana to pll_testout_o
2021-05-22 Luke Kenneth... reduce nc pins by 5 for PLL
2021-05-09 Luke Kenneth... code-comments about ls180 imports
2021-05-03 Luke Kenneth... must only try to connect jtag when variant requests it
2021-05-03 Luke Kenneth... comment that variant for debug must be --variant=standard
2021-04-22 Luke Kenneth... comments on DMI interface
2021-04-20 Luke Kenneth... code-comments for sim.py debug mode
2021-04-18 Luke Kenneth... sort out names
2021-04-18 Luke Kenneth... rename spblock_512 4k sram module to lowercase
2021-04-18 Luke Kenneth... whoops clk_sel_i renamed accidentally
2021-04-18 Luke Kenneth... rename PLL pins to match LIP6.fr PLL
2021-04-18 Luke Kenneth... rename XICS memmap regions
2021-04-18 Luke Kenneth... add SPBlock_512W64B8W.v to sources
2021-04-18 Luke Kenneth... put imports into conditional blocks. makes core.py...
2021-04-18 Luke Kenneth... remove unneeded option
2021-04-18 Luke Kenneth... update to build ls180 4k SRAMs
2021-04-15 Luke Kenneth... got ft232 openocd test working
2021-04-08 Luke Kenneth... reduce jtag data bus width to 32, to match litex
2021-04-06 Luke Kenneth... more experimenting with STLinkv2 openocd
2021-04-05 Luke Kenneth... add stlink directdap config
2021-04-05 Luke Kenneth... hla newtap is apparently the command to run, to request...
2021-04-05 Luke Kenneth... add first version opnocd_stlinkv2.cfg
2021-04-05 Luke Kenneth... sort out sdr and sdmmc OE pad drive, no longer one...
2021-04-01 Luke Kenneth... disable PLL so increase not-connected by another 4...
2021-04-01 Luke Kenneth... remove cocotb, moved to soc-cocotb-sim (as submodule)
2021-04-01 Staf VerhaegenUse correct ir_width for libresoc JTAG TAP.
2021-04-01 Luke Kenneth... whitespace
2021-04-01 Staf VerhaegenDocument c4m-jtag dependency.
2021-04-01 Luke Kenneth... disable PLL for litex build, new variant
2021-04-01 Staf VerhaegenFix svf file for limited c4m-jtag SVF grammar.
2021-04-01 Staf VerhaegenFirst setup for cocotb test run.
2021-03-30 Luke Kenneth... update Makefile to build 4ksrams
2021-03-29 Luke Kenneth... move name of XICS ICS/ICP to match latest litex pythond...
2021-03-29 Luke Kenneth... must not add bus width parameter
2021-03-28 Luke Kenneth... fix issues with port direction on several pads
2021-03-27 Luke Kenneth... latest fighting with litex to get pad directions connec...
2021-03-25 Luke Kenneth... debugging ls180 litex hell
2021-03-22 Luke Kenneth... sort out naming of IOpads for bi-directional pins
2021-03-22 Luke Kenneth... SDR pad mask output for DM
2021-03-12 Luke Kenneth... unneeded file
2021-03-12 Luke Kenneth... splitting out litex files from soc repo into separate...
2021-03-12 Luke Kenneth... first (empty) commit