projects / yosys.git / shortlog
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
yosys.git
2019-07-23 Eddie HungFix muxAB logic commit | commitdiff | tree
2019-07-23 Eddie HungRemove debug print commit | commitdiff | tree
2019-07-23 Eddie HungSimplify and fix for MACs commit | commitdiff | tree
2019-07-23 Eddie HungFix typo commit | commitdiff | tree
2019-07-22 Eddie HungFix spacing commit | commitdiff | tree
2019-07-22 Eddie HungRemove debug commit | commitdiff | tree
2019-07-22 Eddie HungPack hi and lo registers separately commit | commitdiff | tree
2019-07-22 Eddie HungSigSpec::extract() to return as many bits as poss if... commit | commitdiff | tree
2019-07-22 Eddie HungRename according to vendor doc TN1295 commit | commitdiff | tree
2019-07-22 Eddie HungPack Y register commit | commitdiff | tree
2019-07-22 Eddie Hungopt and wreduce necessary for -dsp commit | commitdiff | tree
2019-07-22 Eddie HungPack adders not just accumulators commit | commitdiff | tree
2019-07-22 Eddie HungUse minimum sized width wires commit | commitdiff | tree
2019-07-20 Eddie HungRestore old ffY behaviour commit | commitdiff | tree
2019-07-20 Eddie HungCleanup commit | commitdiff | tree
2019-07-20 Eddie HungIndirection via $__soft_mul commit | commitdiff | tree
2019-07-19 Eddie HungDo not do sign extension in techmap; let packer do it commit | commitdiff | tree
2019-07-19 Eddie HungMerge remote-tracking branch 'origin/eddie/wreduce_add... commit | commitdiff | tree
2019-07-19 Eddie HungAdd another test commit | commitdiff | tree
2019-07-19 Eddie HungDo not access beyond bounds commit | commitdiff | tree
2019-07-19 Eddie HungAdd an SigSpec::at(offset, defval) convenience method commit | commitdiff | tree
2019-07-19 Eddie HungWrap A and B in sigmap commit | commitdiff | tree
2019-07-19 Eddie HungRemove "top" from message commit | commitdiff | tree
2019-07-19 Eddie HungMerge remote-tracking branch 'origin/eddie/wreduce_add... commit | commitdiff | tree
2019-07-19 Eddie HungAlso optimise MSB of $sub commit | commitdiff | tree
2019-07-19 Eddie HungAdd one more test with trimming Y_WIDTH of $sub commit | commitdiff | tree
2019-07-19 Eddie HungBe more explicit commit | commitdiff | tree
2019-07-19 Eddie Hungwreduce for $sub commit | commitdiff | tree
2019-07-19 Eddie HungAdd tests for sub too commit | commitdiff | tree
2019-07-19 Eddie HungAdd test commit | commitdiff | tree
2019-07-19 Eddie HungSigSpec::extract to take negative lengths commit | commitdiff | tree
2019-07-19 Eddie HungDo not $mul -> $__mul if A and B are less than maxwidth commit | commitdiff | tree
2019-07-19 Eddie HungAdd DSP_MINWIDTH=11 for ice40 since ice40_dsp uses... commit | commitdiff | tree
2019-07-19 Eddie HungAdd a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH... commit | commitdiff | tree
2019-07-19 Eddie HungFine tune ice40_dsp.pmg, add support for packing subset... commit | commitdiff | tree
2019-07-19 Eddie HungAdd support for ice40 signed multipliers commit | commitdiff | tree
2019-07-19 Eddie HungMerge branch 'xc7dsp' into ice40dsp commit | commitdiff | tree
2019-07-19 Eddie HungFix typo in B commit | commitdiff | tree
2019-07-19 Eddie HungMerge remote-tracking branch 'origin/eddie/signed_ice40... commit | commitdiff | tree
2019-07-19 David Shahice40: Fix test_dsp_model.sh commit | commitdiff | tree
2019-07-19 David Shahice40/cells_sim.v: Fix sign of J and K partial products commit | commitdiff | tree
2019-07-19 Eddie HungUse sign_headroom instead commit | commitdiff | tree
2019-07-19 David Shahice40/cells_sim.v: LSB of A/B only signed in 8x8 mode commit | commitdiff | tree
2019-07-19 Eddie HungAdd tests for all combinations of A and B signedness... commit | commitdiff | tree
2019-07-19 Eddie HungDon't copy ref if exists already commit | commitdiff | tree
2019-07-19 Eddie HungFix SB_MAC sim model -- do not sign extend internal... commit | commitdiff | tree
2019-07-19 Eddie HungAdd params commit | commitdiff | tree
2019-07-19 Eddie HungMerge remote-tracking branch 'origin/master' into ice40dsp commit | commitdiff | tree
2019-07-19 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp commit | commitdiff | tree
2019-07-18 Eddie HungDo not define `DSP_SIGNEDONLY macro if no exists commit | commitdiff | tree
2019-07-18 Eddie HungMerge remote-tracking branch 'origin/master' into ice40dsp commit | commitdiff | tree
2019-07-18 Eddie Hungice40_dsp to accept $__MUL16X16 too commit | commitdiff | tree
2019-07-18 Eddie Hungsynth_ice40 to decompose into 16x16 commit | commitdiff | tree
2019-07-18 Eddie Hungmul2dsp to create cells that can be interchanged with... commit | commitdiff | tree
2019-07-18 Eddie HungCheck if RHS is empty first commit | commitdiff | tree
2019-07-18 Eddie HungMake consistent commit | commitdiff | tree
2019-07-18 Eddie HungDo not autoremove ffP aor muxP commit | commitdiff | tree
2019-07-18 Eddie HungImprove pattern matcher to match subsets of $dffe?... commit | commitdiff | tree
2019-07-18 Eddie HungImprove A/B reg packing commit | commitdiff | tree
2019-07-18 Eddie HungDo not autoremove A/B registers since they might have... commit | commitdiff | tree
2019-07-18 Eddie HungFix xilinx_dsp index cast commit | commitdiff | tree
2019-07-18 Eddie HungFix signed multiplier decomposition commit | commitdiff | tree
2019-07-18 Eddie HungUse single DSP_SIGNEDONLY macro commit | commitdiff | tree
2019-07-18 David ShahMerge pull request #1208 from ZirconiumX/intel_cleanups commit | commitdiff | tree
2019-07-18 Dan Ravensloftsynth_intel: Use stringf commit | commitdiff | tree
2019-07-18 Eddie HungWorking for unsigned commit | commitdiff | tree
2019-07-18 David ShahMerge pull request #1207 from ZirconiumX/intel_new_pass... commit | commitdiff | tree
2019-07-18 Dan Ravensloftsynth_intel: s/not family/no family/ commit | commitdiff | tree
2019-07-18 Eddie HungCleanup commit | commitdiff | tree
2019-07-18 Dan Ravensloftsynth_intel: revert change to run_max10 commit | commitdiff | tree
2019-07-18 Ben Widawskyintel_synth: Fix help message commit | commitdiff | tree
2019-07-18 Ben Widawskyintel_synth: Small code cleanup to remove if ladder commit | commitdiff | tree
2019-07-18 Ben Widawskyintel_synth: Make family explicit and match commit | commitdiff | tree
2019-07-18 Ben Widawskyintel_synth: Minor code cleanups commit | commitdiff | tree
2019-07-18 Dan Ravensloftsynth_intel: rename for consistency with #1184 commit | commitdiff | tree
2019-07-18 Eddie HungWrong wildcard symbol commit | commitdiff | tree
2019-07-18 Eddie HungMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into... commit | commitdiff | tree
2019-07-18 Clifford WolfMerge pull request #1184 from whitequark/synth-better... commit | commitdiff | tree
2019-07-18 Clifford WolfMerge pull request #1203 from whitequark/write_verilog... commit | commitdiff | tree
2019-07-18 David Shahmul2dsp: Lower partial products always have unsigned... commit | commitdiff | tree
2019-07-17 Eddie HungMake all operands signed commit | commitdiff | tree
2019-07-17 Eddie HungUpdate comment commit | commitdiff | tree
2019-07-17 Eddie HungPattern matcher to check pool of bits, not exactly commit | commitdiff | tree
2019-07-17 Eddie HungFix mul2dsp signedness commit | commitdiff | tree
2019-07-17 Eddie HungA_SIGNED == B_SIGNED so flip both commit | commitdiff | tree
2019-07-17 Eddie HungSigSpec::remove_const() to return SigSpec& commit | commitdiff | tree
2019-07-17 Clifford WolfRemove old $pmux_safe code from write_verilog commit | commitdiff | tree
2019-07-17 David ShahMerge pull request #1204 from smunaut/fix_1187 commit | commitdiff | tree
2019-07-16 Eddie HungAdd DSP_{A,B}_SIGNEDONLY macro commit | commitdiff | tree
2019-07-16 Eddie HungSignedness commit | commitdiff | tree
2019-07-16 Eddie HungSigned extension commit | commitdiff | tree
2019-07-16 Sylvain Munautice40: Adapt the relut process passes to the new $lut... commit | commitdiff | tree
2019-07-16 Eddie HungRevert drop down to 24x16 multipliers for all commit | commitdiff | tree
2019-07-16 Eddie HungMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into... commit | commitdiff | tree
2019-07-16 Eddie HungAdd support {A,B,P}REG packing commit | commitdiff | tree
2019-07-16 Eddie HungSigSpec::extract to allow negative length commit | commitdiff | tree
2019-07-16 Eddie HungAdd support for {A,B,P}REG in DSP48E1 commit | commitdiff | tree
2019-07-16 whitequarkwrite_verilog: dump zero width constants correctly. commit | commitdiff | tree
2019-07-16 Eddie HungMerge pull request #1202 from YosysHQ/cmp2lut_lut6 commit | commitdiff | tree
2019-07-16 whitequarksynth_ecp5: rename dram to lutram everywhere. commit | commitdiff | tree
next