| 2019-06-04 |
whitequark | vendor.board.tinyfpga_bx: fix typo. |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.conn.pmod: implement. |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | examples: reorganize into examples/basic and examples... |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.board: extract package. |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.tinyfpga_bx: add connectors. |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.icestick: add connectors. |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.ice40_hx1k_blink_evn: add (some) connectors. |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | build.{plat,res}: add support for connectors. |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | build.dsl: add support for connectors. |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | compat.fhdl.specials: TSTriple is not an elaboratable. |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: implement differential outpu... |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: implement differential input... |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: allow instantiating SB_GB_IO... |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: implement SDR and DDR I... |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | lib.io: add i_clk and o_clk to pin layout with xdr>=1. |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | hdl.rec: unbreak hasattr(rec, ...). |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | build.{dsl,plat,res}: allow dir="oe". |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | lib.io: allow dir="oe". |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | build.{res,plat}: use xdr=0 as default, not xdr=1. |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | build.res: allow requesting raw ports, with dir="-". |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | lib.io: allow Pin(xdr=0), representing a combinatorial... |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: enable SystemVerilog when... |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | build.res: if not specified, request resource #0. |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | vendor.fpga.lattice_ice40: instantiate SB_IO and apply... |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | hdl.ir: accept LHS signals like slices as Instance... |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | hdl.dsl: allow adding submodules with computed name... |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | hdl.ir: accept expanded (kind, name, value) tuples... |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | build.{res,plat}: propagate extras to pin fragment... |
commit | commitdiff | tree |
| 2019-06-03 |
whitequark | build.res: simplify. NFC. |
commit | commitdiff | tree |
| 2019-06-02 |
whitequark | build.dsl: require a dict for extras instead of a strin... |
commit | commitdiff | tree |
| 2019-06-02 |
whitequark | vendor.fpga.lattice_ice40: use .bin suffix for bitstrea... |
commit | commitdiff | tree |
| 2019-06-02 |
whitequark | vendor.tinyfpga_{b→bx} |
commit | commitdiff | tree |
| 2019-06-02 |
whitequark | vendor.tinyfpga_b: fix IO_STANDARD. |
commit | commitdiff | tree |
| 2019-06-02 |
Simon Kirkby | vendor.tinyfpga_b: implement. |
commit | commitdiff | tree |
| 2019-06-02 |
whitequark | vendor.icestick: fix typo. |
commit | commitdiff | tree |
| 2019-06-01 |
whitequark | Travis: update install script. |
commit | commitdiff | tree |
| 2019-06-01 |
whitequark | vendor.ice40_hx1k_blink_evn: implement. |
commit | commitdiff | tree |
| 2019-06-01 |
whitequark | vendor.icestick: implement. |
commit | commitdiff | tree |
| 2019-06-01 |
whitequark | vendor.fpga.lattice_ice40: implement. |
commit | commitdiff | tree |
| 2019-06-01 |
whitequark | build.plat: implement. |
commit | commitdiff | tree |
| 2019-06-01 |
whitequark | build.res: always return a Pin record. |
commit | commitdiff | tree |
| 2019-06-01 |
whitequark | build.res: accept a list of clocks in ConstraintManager... |
commit | commitdiff | tree |
| 2019-05-26 |
whitequark | back.rtlil: allow specifying platform for convert(). |
commit | commitdiff | tree |
| 2019-05-26 |
whitequark | Add versioneer. |
commit | commitdiff | tree |
| 2019-05-26 |
whitequark | hdl.ir: silence unused elaboratable warning on interpre... |
commit | commitdiff | tree |
| 2019-05-26 |
Jean-François... | build.res: add ConstraintManager. |
commit | commitdiff | tree |
| 2019-05-25 |
whitequark | build.dsl: make Pins and DiffPairs iterable. |
commit | commitdiff | tree |
| 2019-05-25 |
whitequark | build.dsl: improve repr of Pins() and DiffPairs(). |
commit | commitdiff | tree |
| 2019-05-25 |
whitequark | hdl.rec: allow providing fields during construction. |
commit | commitdiff | tree |
| 2019-05-25 |
whitequark | Consider Instances a part of containing fragment for... |
commit | commitdiff | tree |
| 2019-05-20 |
Chris Osterwood | Add import so that Tristate.elaborate builds |
commit | commitdiff | tree |
| 2019-05-15 |
whitequark | hdl.ir: when adding sync domain to a design, also add... |
commit | commitdiff | tree |
| 2019-05-13 |
whitequark | hdl.ir: during port propagation, defs should take prior... |
commit | commitdiff | tree |
| 2019-05-13 |
whitequark | back.rtlil: assign undriven signals to their reset... |
commit | commitdiff | tree |
| 2019-05-12 |
whitequark | hdl: make all public Value classes other than Record... |
commit | commitdiff | tree |
| 2019-05-12 |
whitequark | hdl.ir: only pull explicitly specified ports to topleve... |
commit | commitdiff | tree |
| 2019-04-24 |
Jean-François... | lib.io: add a name argument to the Pin constructor. |
commit | commitdiff | tree |
| 2019-04-24 |
whitequark | build.dsl: style. NFC. |
commit | commitdiff | tree |
| 2019-04-24 |
Jean-François... | build: add DSL for defining platform resources. |
commit | commitdiff | tree |
| 2019-04-22 |
whitequark | back.verilog: allow stripping the src attribute, for... |
commit | commitdiff | tree |
| 2019-04-22 |
Alain Péteut | compat.fhdl.specials: fix Tristate, TSTriple. |
commit | commitdiff | tree |
| 2019-04-22 |
Alain Péteut | compat.fhdl.specials: fix Tristate. |
commit | commitdiff | tree |
| 2019-04-22 |
whitequark | compat.fhdl.specials: fix TSTriple. |
commit | commitdiff | tree |
| 2019-04-22 |
whitequark | hdl.ir: rework named port handling for Instances. |
commit | commitdiff | tree |
| 2019-04-21 |
whitequark | Remove examples/tbuf.py. |
commit | commitdiff | tree |
| 2019-04-21 |
whitequark | hdl.ir: detect elaboratables that are created but not... |
commit | commitdiff | tree |
| 2019-04-21 |
whitequark | back.rtlil: emit `nmigen.hierarchy` attribute. |
commit | commitdiff | tree |
| 2019-04-21 |
whitequark | hdl.ast: improve tests for exceptional conditions. |
commit | commitdiff | tree |
| 2019-04-21 |
whitequark | hdl.ast: accept Signals with identical min/max bounds. |
commit | commitdiff | tree |
| 2019-04-21 |
whitequark | back.rtlil: only expand legalized values in Array/Part... |
commit | commitdiff | tree |
| 2019-04-21 |
whitequark | hdl.rec: implement Record.connect. |
commit | commitdiff | tree |
| 2019-04-20 |
whitequark | back.rtlil: allow record slices on LHS. |
commit | commitdiff | tree |
| 2019-04-19 |
whitequark | hdl.rec: fix slicing of records. |
commit | commitdiff | tree |
| 2019-04-18 |
whitequark | hdl.xfrm: handle classes that inherit from Record. |
commit | commitdiff | tree |
| 2019-04-15 |
whitequark | lib.io: rework TSTriple/Tristate interface to use pin_l... |
commit | commitdiff | tree |
| 2019-04-10 |
whitequark | hdl.ast: fix some type checks. |
commit | commitdiff | tree |
| 2019-04-10 |
whitequark | hdl.xfrm: allow using FragmentTransformer on any elabor... |
commit | commitdiff | tree |
| 2019-04-09 |
whitequark | hdl: remove deprecated get_fragment() and lower() methods. |
commit | commitdiff | tree |
| 2019-04-03 |
whitequark | hdl.ast: handle a common typo, such as Signal(1, True). |
commit | commitdiff | tree |
| 2019-03-28 |
whitequark | test_sim: add missing add_process(). |
commit | commitdiff | tree |
| 2019-03-28 |
Luke Wren | lib.cdc: add optional reset to MultiReg, and document... |
commit | commitdiff | tree |
| 2019-03-28 |
whitequark | back.rtlil: fix off-by-one in Part legalization. |
commit | commitdiff | tree |
| 2019-03-25 |
anuejn | hdl.rec: separate record and signal name with __, not _. |
commit | commitdiff | tree |
| 2019-03-25 |
whitequark | hdl.ast: fix typo. |
commit | commitdiff | tree |
| 2019-03-12 |
Alain Péteut | examples.por: fix typo |
commit | commitdiff | tree |
| 2019-03-03 |
whitequark | lib.fifo: register GrayEncoder output before CDC. |
commit | commitdiff | tree |
| 2019-03-03 |
whitequark | tracer: factor out get_var_name(default=). |
commit | commitdiff | tree |
| 2019-03-03 |
whitequark | hdl.rec: remove __slots__. |
commit | commitdiff | tree |
| 2019-02-22 |
Alain Péteut | setup.py: constrain Python version |
commit | commitdiff | tree |
| 2019-02-14 |
whitequark | hdl.ir: raise a more descriptive error on non-elaborata... |
commit | commitdiff | tree |
| 2019-01-26 |
whitequark | back.rtlil: accept ast.Const as cell parameter. |
commit | commitdiff | tree |
| 2019-01-26 |
whitequark | hdl.ast: fix ValueKey for Cat. |
commit | commitdiff | tree |
| 2019-01-26 |
whitequark | compat.fhdl.module: fix typo. |
commit | commitdiff | tree |
| 2019-01-26 |
whitequark | compat.fhdl.specials: fix __all__ list. |
commit | commitdiff | tree |
| 2019-01-26 |
whitequark | compat.genlib.resetsync: add shim for AsyncResetSynchro... |
commit | commitdiff | tree |
| 2019-01-26 |
whitequark | compat.fifo: fix _FIFOInterface deprecation wrapper. |
commit | commitdiff | tree |
| 2019-01-26 |
whitequark | lib.cdc: add ResetSynchronizer. |
commit | commitdiff | tree |
| 2019-01-26 |
whitequark | back.pysim: support async reset. |
commit | commitdiff | tree |
| 2019-01-26 |
whitequark | back.pysim: give better names to unnamed fragments... |
commit | commitdiff | tree |
| 2019-01-26 |
whitequark | examples: update for newer API. |
commit | commitdiff | tree |
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projects / nmigen.git / shortlog