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litex.git
2011-12-10
Sebastien Bourdeauducq
fhdl: pad support in fragments
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2011-12-09
Sebastien Bourdeauducq
wishbone: decoder + shared bus interconnect
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2011-12-09
Sebastien Bourdeauducq
fhdl: replication support
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2011-12-08
Sebastien Bourdeauducq
wishbone: arbiter
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2011-12-08
Sebastien Bourdeauducq
simplebus: export GetSigName function
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2011-12-08
Sebastien Bourdeauducq
corelogic: multimux module
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2011-12-08
Sebastien Bourdeauducq
verilog: handle default in case statements
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2011-12-08
Sebastien Bourdeauducq
fhdl: improve automatic signal naming
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2011-12-08
Sebastien Bourdeauducq
Corelogic conversion example
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2011-12-08
Sebastien Bourdeauducq
corelogic: MC divider module
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2011-12-08
Sebastien Bourdeauducq
fhdl: support negation operator
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2011-12-08
Sebastien Bourdeauducq
verilog: fix unary operator conversion
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2011-12-08
Sebastien Bourdeauducq
corelogic: round-robin module
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2011-12-08
Sebastien Bourdeauducq
Named buses
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2011-12-08
Sebastien Bourdeauducq
wishbone: add missing SEL
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2011-12-08
Sebastien Bourdeauducq
instances: signal override
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2011-12-08
Sebastien Bourdeauducq
Wishbone declarations
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2011-12-08
Sebastien Bourdeauducq
Simple bus base class
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2011-12-08
Sebastien Bourdeauducq
Instance support
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2011-12-07
Sebastien Bourdeauducq
fhdl: fix implicit slice index
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2011-12-07
Sebastien Bourdeauducq
fhdl: cleanup value bv
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2011-12-05
Sebastien Bourdeauducq
Variable conversion
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2011-12-05
Sebastien Bourdeauducq
Cleanup
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2011-12-05
Sebastien Bourdeauducq
Case support + register bank generator
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2011-12-04
Sebastien Bourdeauducq
CSR bus definitions
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2011-12-04
Sebastien Bourdeauducq
Examples folder
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2011-12-04
Sebastien Bourdeauducq
Reset insertion
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2011-12-04
Sebastien Bourdeauducq
Verilog generator
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2011-12-04
Sebastien Bourdeauducq
Initial import, FHDL basic structure, divider example
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