| 2019-12-13 |
Eddie Hung | Disable RAM16X1D test |
commit | commitdiff | tree |
| 2019-12-13 |
Eddie Hung | Disable RAM16X1D match rule; carry-over from LUT4 arches |
commit | commitdiff | tree |
| 2019-12-13 |
Eddie Hung | RAM64M8 to also have [5:0] for address |
commit | commitdiff | tree |
| 2019-12-13 |
Eddie Hung | Remove extraneous synth_xilinx call |
commit | commitdiff | tree |
| 2019-12-13 |
Eddie Hung | Add tests for these new models |
commit | commitdiff | tree |
| 2019-12-13 |
Eddie Hung | Add RAM32X6SDP and RAM64X3SDP modes |
commit | commitdiff | tree |
| 2019-12-13 |
Eddie Hung | Fix RAM64M model to have 6 bit address bus |
commit | commitdiff | tree |
| 2019-12-13 |
Eddie Hung | Add #1460 testcase |
commit | commitdiff | tree |
| 2019-12-13 |
Eddie Hung | Add memory rules for RAM16X1D, RAM32M, RAM64M |
commit | commitdiff | tree |
| 2019-12-13 |
Eddie Hung | Rename memory tests to lutram, add more xilinx tests |
commit | commitdiff | tree |
| 2019-12-12 |
Eddie Hung | abc9_map.v: fix Xilinx LUTRAM |
commit | commitdiff | tree |
| 2019-12-12 |
Eddie Hung | Update README.md :: abc_ -> abc9_ |
commit | commitdiff | tree |
| 2019-12-11 |
Eddie Hung | Fix bitwidth mismatch; suppresses iverilog warning |
commit | commitdiff | tree |
| 2019-12-11 |
David Shah | Merge pull request #1564 from ZirconiumX/intel_housekeeping |
commit | commitdiff | tree |
| 2019-12-10 |
Dan Ravensloft | synth_intel: a10gx -> arria10gx |
commit | commitdiff | tree |
| 2019-12-10 |
Dan Ravensloft | synth_intel: cyclone10 -> cyclone10lp |
commit | commitdiff | tree |
| 2019-12-10 |
Eddie Hung | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapc... |
commit | commitdiff | tree |
| 2019-12-09 |
Eddie Hung | ice40_opt to restore attributes/name when unwrapping |
commit | commitdiff | tree |
| 2019-12-09 |
Eddie Hung | ice40_wrapcarry -unwrap to preserve 'src' attribute |
commit | commitdiff | tree |
| 2019-12-09 |
Eddie Hung | unmap $__ICE40_CARRY_WRAPPER in test |
commit | commitdiff | tree |
| 2019-12-09 |
Eddie Hung | -unwrap to create $lut not SB_LUT4 for opt_lut |
commit | commitdiff | tree |
| 2019-12-09 |
Eddie Hung | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER... |
commit | commitdiff | tree |
| 2019-12-09 |
Eddie Hung | ice40_wrapcarry to really preserve attributes via ... |
commit | commitdiff | tree |
| 2019-12-07 |
Eddie Hung | Merge pull request #1555 from antmicro/fix-macc-xilinx... |
commit | commitdiff | tree |
| 2019-12-07 |
Eddie Hung | Drop keep=0 attributes on SB_CARRY |
commit | commitdiff | tree |
| 2019-12-06 |
Jan Kowalewski | tests: arch: xilinx: Change order of arguments in macc.sh |
commit | commitdiff | tree |
| 2019-12-05 |
Clifford Wolf | Merge pull request #1551 from whitequark/manual-cell... |
commit | commitdiff | tree |
| 2019-12-05 |
Eddie Hung | Merge SB_CARRY+SB_LUT4's attributes when creating ... |
commit | commitdiff | tree |
| 2019-12-05 |
Eddie Hung | Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER |
commit | commitdiff | tree |
| 2019-12-04 |
whitequark | kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, ... |
commit | commitdiff | tree |
| 2019-12-04 |
whitequark | manual: document behavior of many comb cells more preci... |
commit | commitdiff | tree |
| 2019-12-04 |
Marcin Kościelnicki | xilinx: Add tristate buffer mapping. (#1528) |
commit | commitdiff | tree |
| 2019-12-04 |
Marcin Kościelnicki | iopadmap: Refactor and fix tristate buffer mapping... |
commit | commitdiff | tree |
| 2019-12-04 |
Marcin Kościelnicki | xilinx: Add models for LUTRAM cells. (#1537) |
commit | commitdiff | tree |
| 2019-12-03 |
Eddie Hung | Check SB_CARRY name also preserved |
commit | commitdiff | tree |
| 2019-12-03 |
Eddie Hung | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for... |
commit | commitdiff | tree |
| 2019-12-03 |
Eddie Hung | ice40_opt to ignore (* keep *) -ed cells |
commit | commitdiff | tree |
| 2019-12-03 |
Eddie Hung | ice40_wrapcarry to preserve SB_CARRY's attributes |
commit | commitdiff | tree |
| 2019-12-03 |
Eddie Hung | Add testcase |
commit | commitdiff | tree |
| 2019-12-03 |
Clifford Wolf | Merge pull request #1524 from pepijndevos/gowindffinit |
commit | commitdiff | tree |
| 2019-12-03 |
Pepijn de Vos | update test |
commit | commitdiff | tree |
| 2019-12-03 |
Pepijn de Vos | Use -match-init to not synth contradicting init values |
commit | commitdiff | tree |
| 2019-12-02 |
David Shah | Merge pull request #1542 from YosysHQ/dave/abc9-loop-fix |
commit | commitdiff | tree |
| 2019-12-02 |
Clifford Wolf | Merge pull request #1539 from YosysHQ/mwk/ilang-bounds... |
commit | commitdiff | tree |
| 2019-12-01 |
David Shah | abc9: Fix breaking of SCCs |
commit | commitdiff | tree |
| 2019-11-29 |
Miodrag Milanović | Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll |
commit | commitdiff | tree |
| 2019-11-29 |
Marcin Kościelnicki | xilinx: Add missing blackbox cell for BUFPLL. |
commit | commitdiff | tree |
| 2019-11-28 |
Eddie Hung | Revert "Fold loop" |
commit | commitdiff | tree |
| 2019-11-27 |
Marcin Kościelnicki | read_ilang: do bounds checking on bit indices |
commit | commitdiff | tree |
| 2019-11-27 |
Eddie Hung | Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_... |
commit | commitdiff | tree |
| 2019-11-27 |
Clifford Wolf | Merge pull request #1501 from YosysHQ/dave/mem_copy_attr |
commit | commitdiff | tree |
| 2019-11-27 |
Clifford Wolf | Merge pull request #1534 from YosysHQ/mwk/opt_share-fix |
commit | commitdiff | tree |
| 2019-11-27 |
Eddie Hung | Merge pull request #1535 from YosysHQ/eddie/write_xaige... |
commit | commitdiff | tree |
| 2019-11-27 |
Eddie Hung | No need for -abc9 |
commit | commitdiff | tree |
| 2019-11-27 |
Marcin Kościelnicki | opt_share: Fix handling of fine cells. |
commit | commitdiff | tree |
| 2019-11-27 |
Eddie Hung | latch -> box |
commit | commitdiff | tree |
| 2019-11-27 |
Eddie Hung | Add citation |
commit | commitdiff | tree |
| 2019-11-27 |
Eddie Hung | Check for either sign or zero extension for postAdd... |
commit | commitdiff | tree |
| 2019-11-27 |
Eddie Hung | Remove notes |
commit | commitdiff | tree |
| 2019-11-27 |
Eddie Hung | Fold loop |
commit | commitdiff | tree |
| 2019-11-27 |
Eddie Hung | Do not sigmap keep bits inside write_xaiger |
commit | commitdiff | tree |
| 2019-11-27 |
Eddie Hung | xaiger: do not promote output wires |
commit | commitdiff | tree |
| 2019-11-27 |
Eddie Hung | Add testcase derived from fastfir_dynamictaps benchmark |
commit | commitdiff | tree |
| 2019-11-26 |
Marcin Kościelnicki | xilinx: Add simulation models for IOBUF and OBUFT. |
commit | commitdiff | tree |
| 2019-11-25 |
Marcin Kościelnicki | clkbufmap: Add support for inverters in clock path. |
commit | commitdiff | tree |
| 2019-11-25 |
Marcin Kościelnicki | xilinx: Use INV instead of LUT1 when applicable |
commit | commitdiff | tree |
| 2019-11-25 |
Pepijn de Vos | attempt to fix formatting |
commit | commitdiff | tree |
| 2019-11-25 |
Pepijn de Vos | gowin: add and test dff init values |
commit | commitdiff | tree |
| 2019-11-23 |
Eddie Hung | Merge pull request #1520 from pietrmar/fix-1463 |
commit | commitdiff | tree |
| 2019-11-23 |
Martin Pietryka | coolrunner2: remove spurious log_pop() call, fixes... |
commit | commitdiff | tree |
| 2019-11-22 |
Clifford Wolf | Merge pull request #1517 from YosysHQ/clifford/optmem |
commit | commitdiff | tree |
| 2019-11-22 |
Clifford Wolf | Merge pull request #1515 from YosysHQ/clifford/svastuff |
commit | commitdiff | tree |
| 2019-11-22 |
Clifford Wolf | Add "opt_mem" pass |
commit | commitdiff | tree |
| 2019-11-22 |
Clifford Wolf | Add Verific support for SVA nexttime properties |
commit | commitdiff | tree |
| 2019-11-22 |
Clifford Wolf | Improve handling of verific primitives in "verific... |
commit | commitdiff | tree |
| 2019-11-22 |
Clifford Wolf | Add Verific SVA support for "always" properties |
commit | commitdiff | tree |
| 2019-11-22 |
Clifford Wolf | Merge pull request #1511 from YosysHQ/dave/always |
commit | commitdiff | tree |
| 2019-11-22 |
Marcin Kościelnicki | gowin: Remove show command from tests. |
commit | commitdiff | tree |
| 2019-11-22 |
Marcin Kościelnicki | gowin: Add missing .gitignore entries |
commit | commitdiff | tree |
| 2019-11-22 |
David Shah | Update CHANGELOG and README |
commit | commitdiff | tree |
| 2019-11-21 |
David Shah | sv: Add tests for SV always types |
commit | commitdiff | tree |
| 2019-11-21 |
David Shah | proc_dlatch: Add error handling for incorrect always_... |
commit | commitdiff | tree |
| 2019-11-21 |
David Shah | sv: Correct parsing of always_comb, always_ff and alway... |
commit | commitdiff | tree |
| 2019-11-20 |
Clifford Wolf | Merge pull request #1507 from YosysHQ/clifford/verificfixes |
commit | commitdiff | tree |
| 2019-11-20 |
Clifford Wolf | Correctly treat empty modules as blackboxes in Verific |
commit | commitdiff | tree |
| 2019-11-20 |
Clifford Wolf | Do not rename VHDL entities to "entity(impl)" when... |
commit | commitdiff | tree |
| 2019-11-19 |
Clifford Wolf | Merge pull request #1449 from pepijndevos/gowin |
commit | commitdiff | tree |
| 2019-11-19 |
Pepijn de Vos | Remove dff init altogether |
commit | commitdiff | tree |
| 2019-11-19 |
Marcin Kościelnicki | Fix #1462, #1480. |
commit | commitdiff | tree |
| 2019-11-19 |
Marcin Kościelnicki | xilinx: Add simulation models for MULT18X18* and DSP48A*. |
commit | commitdiff | tree |
| 2019-11-18 |
David Shah | memory_collect: Copy attr from RTLIL::Memory to cell |
commit | commitdiff | tree |
| 2019-11-18 |
Pepijn de Vos | add help for nowidelut and abc9 options |
commit | commitdiff | tree |
| 2019-11-18 |
Clifford Wolf | Merge pull request #1497 from YosysHQ/mwk/extract-fa-fix |
commit | commitdiff | tree |
| 2019-11-18 |
whitequark | Merge pull request #1494 from whitequark/write_verilog... |
commit | commitdiff | tree |
| 2019-11-18 |
Marcin Kościelnicki | Fix #1496. |
commit | commitdiff | tree |
| 2019-11-18 |
whitequark | write_verilog: add -extmem option, to write split memor... |
commit | commitdiff | tree |
| 2019-11-17 |
Clifford Wolf | Merge pull request #1492 from YosysHQ/dave/wreduce... |
commit | commitdiff | tree |
| 2019-11-16 |
Pepijn de Vos | Merge branch 'master' of https://github.com/YosysHQ... |
commit | commitdiff | tree |
| 2019-11-15 |
David Shah | ecp5: Use new autoname pass for better cell/net names |
commit | commitdiff | tree |
| 2019-11-14 |
David Shah | wreduce: Don't trim zeros or sext when not matching... |
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