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yosys.git
2021-04-21
Claire Xen
Merge pull request #2669 from YosysHQ/claire/ice40defaults
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2021-04-20
Claire Xenia...
Add default assignments to other SB_* simulation models
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2021-04-20
Claire Xenia...
Add default assignments to SB_LUT4
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2021-04-17
Lofty
quicklogic: ABC9 synthesis
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2021-04-09
Stefan Riesenberger
sf2: fix name of AND modules
ls180
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2021-04-09
whitequark
Merge pull request #2724 from whitequark/flatten-rewrit...
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2021-04-09
whitequark
flatten: rewrite memid in memwr actions.
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2021-03-30
Zachary Snow
preproc: test coverage for #2712
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2021-03-30
Marcelina Kościelnicka
equiv: Suggest running async2sync or clk2fflogic where...
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2021-03-30
Zachary Snow
verilog: revise hot comment warnings
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2021-03-30
Eddie Hung
abc9: uniquify blackboxes like whiteboxes (#2695)
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2021-03-30
Eddie Hung
abc9: fix SCC issues (#2694)
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2021-03-30
Marcelina Kościelnicka
Bump version
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2021-03-30
Marcelina Kościelnicka
preproc: Fix up conditional handling.
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2021-03-29
Zachary Snow
gha: trim macOS dependencies
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2021-03-28
Zachary Snow
gha: combine jobs using matrix
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2021-03-25
Zachary Snow
rtlil: add const accessors for modules, wires, and...
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2021-03-24
whitequark
Merge pull request #2702 from modwizcode/patch-1
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2021-03-24
Iris Johnson
Clarify bugpoint documentation regarding output
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2021-03-24
Zachary Snow
ast: make design available to process_module()
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2021-03-23
Marcelina Kościelnicka
rtlil: Fix process memwr roundtrip.
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2021-03-23
N. Engelhardt
Merge pull request #2696 from nakengelhardt/guidelines
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2021-03-23
Marcelina Kościelnicka
quicklogic: Add .gitignore file for test outputs.
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2021-03-23
Marcelina Kościelnicka
json: Improve the "processes in module" message a bit.
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2021-03-22
N. Engelhardt
split CodingReadme into multiple files
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2021-03-21
Xiretza
verilog: check entire user type stack for type definition
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2021-03-19
Zachary Snow
sv: allow typenames as function return types
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2021-03-19
Miodrag Milanović
Merge pull request #2681 from msinger/fix-issue2606
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2021-03-19
Xiretza
verilog: rebuild user_type_stack from globals before...
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2021-03-18
Marcelina Kościelnicka
Add simple CI using github actions.
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2021-03-18
Xiretza
modtools: fix use-after-free of cell pointers in ModWalker
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2021-03-18
Lofty
quicklogic: PolarPro 3 support
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2021-03-17
Marcelina Kościelnicka
ast: Use better parameter serialization for paramod...
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2021-03-17
Michael Singer
Fix check for bad std::regex (fixes #2606)
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2021-03-17
gatecat
Blackbox all whiteboxes after synthesis
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2021-03-17
Zachary Snow
bugpoint: add runner option
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2021-03-17
Zachary Snow
sv: carry over global typedefs from previous files
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2021-03-17
Xiretza
verilog: fix buf/not primitives with multiple outputs
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2021-03-17
gatecat
blackbox: Include whiteboxed modules
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2021-03-17
Lofty
Replace assert in get_reference with more useful error...
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2021-03-16
Zachary Snow
verilog: support module scope identifiers in parametric...
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2021-03-15
Marcelina Kościelnicka
json: Add support for memories.
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2021-03-15
Marcelina Kościelnicka
proc_arst: Add special-casing of clock signal in condit...
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2021-03-15
Marcelina Kościelnicka
opt_clean: Remove init attribute bits together with...
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2021-03-15
Marcelina Kościelnicka
rtlil: Disallow 0-width chunks in SigSpec.
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2021-03-14
whitequark
Merge pull request #2658 from zachjs/parameters-across...
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2021-03-12
Zachary Snow
sv: allow globals in one file to depend on globals...
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2021-03-12
whitequark
Merge pull request #2653 from zachjs/global-parameter
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2021-03-11
whitequark
Merge pull request #2642 from whitequark/cxxrtl-noproc...
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2021-03-11
Zachary Snow
verilog: disallow overriding global parameters
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2021-03-11
Miodrag Milanovic
Add _pm.h files to GENLIST, fixes vcxsrc target
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2021-03-10
Dan Ravensloft
Replace assert in xaiger with more useful error message
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2021-03-09
whitequark
Merge pull request #2643 from zachjs/fix-param-no-defau...
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2021-03-08
Marcelina Kościelnicka
Bump version
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2021-03-08
Marcelina Kościelnicka
memory_dff: Remove now-useless write port handling.
working-ls180
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2021-03-08
Marcelina Kościelnicka
verilog: Use proc memory writes in the frontend.
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2021-03-08
Marcelina Kościelnicka
Add support for memory writes in processes.
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2021-03-08
Marcelina Kościelnicka
sim: Avoid a crash on empty cell connection.
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2021-03-08
Marcelina Kościelnicka
proc_dff: Fix emitted FF when a register is not assigne...
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2021-03-08
Marcelina Kościelnicka
memory_dff: Remove code looking for $mux cells.
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2021-03-08
Marcelina Kościelnicka
tests/bram: Do not generate write address collisions.
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2021-03-07
Zachary Snow
Fix param without default log line
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2021-03-07
Dan Ravensloft
Replace assert in abc9_ops with more useful error message
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2021-03-07
whitequark
cxxrtl: don't assert on edge sync rules tied to a constant.
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2021-03-07
whitequark
cxxrtl: allow `always` sync rules in debug_eval.
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2021-03-07
whitequark
Merge pull request #2626 from zachjs/param-no-default
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2021-03-07
whitequark
Merge pull request #2632 from zachjs/width-limit
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2021-03-06
Zachary Snow
sv: fix some edge cases for unbased unsized literals
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2021-03-06
Marcelina Kościelnicka
proc_clean: Fix empty case removal conditions.
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2021-03-06
Marcelina Kościelnicka
Remove a few functions that, in fact, did not exist...
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2021-03-05
Dan Ravensloft
Replace assert in addModule with more useful error...
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2021-03-05
whitequark
Merge pull request #2635 from whitequark/cxxrtl-memrd...
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2021-03-05
whitequark
Merge pull request #2634 from whitequark/cxxrtl-debug...
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2021-03-05
whitequark
Merge pull request #2633 from whitequark/cxxrtl-no-top
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2021-03-05
whitequark
cxxrtl: follow aliases to outlines when emitting $memrd...
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2021-03-05
whitequark
cxxrtl: add pass debug flag to show assigned wire types.
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2021-03-05
whitequark
cxxrtl: don't crash on empty designs.
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2021-03-04
Zachary Snow
verilog: impose limit on maximum expression width
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2021-03-04
Claire Xen
Update command-reference-manual.tex
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2021-03-04
Claire Xen
Update README
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2021-03-02
Zachary Snow
sv: support for parameters without default values
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2021-03-02
whitequark
Merge pull request #2620 from zachjs/port-int-types
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2021-03-01
Zachary Snow
verilog: fix sizing of ports with int types in module...
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2021-03-01
Marcelina Kościelnicka
Bump version
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2021-03-01
Zachary Snow
verilog: fix handling of nested ifdef directives
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2021-03-01
Zachary Snow
Set aside extraneous tests in simple_abc9 test suite
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2021-03-01
Claire Xen
Merge pull request #2523 from tomverbeure/define_synthesis
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2021-03-01
Claire Xen
Merge pull request #2524 from bkbncn/patch-1
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2021-03-01
whitequark
Merge pull request #2617 from RobertBaruch/doc
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2021-03-01
whitequark
Merge pull request #2615 from zachjs/genrtlil-conflict
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2021-03-01
whitequark
Merge pull request #2618 from zachjs/int-types
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2021-02-28
Zachary Snow
sv: extended support for integer types
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2021-02-27
Robert Baruch
RTLIL Documentation: switch in process is optional
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2021-02-27
Claire Xen
Update issue_template.md
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2021-02-26
Zachary Snow
genrtlil: improve name conflict error messaging
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2021-02-26
Michael Singer
Add tests for $countbits
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2021-02-26
Michael Singer
Implement $countones, $isunknown and $onehot{,0}
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2021-02-26
Michael Singer
Implement $countbits function
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2021-02-26
Zachary Snow
Extend simplify() recursion warning
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2021-02-25
Marcelina Kościelnicka
Bump version
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