yosys.git
2019-12-06 Eddie Hungwrite_xaiger to support part-selected modules again
2019-12-06 Eddie Hungabc9 to do clock partitioning again
2019-12-06 Eddie HungRemove clkpart
2019-12-05 Eddie HungRevert "Special abc9_clock wire to contain only clock...
2019-12-05 Eddie HungMissing wire declaration
2019-12-05 Eddie Hungabc9_map.v to transform INIT=1 to INIT=0
2019-12-05 Eddie HungOh deary me
2019-12-05 Eddie HungBump ABC to get "&verify -s" fix
2019-12-05 Eddie Hungoutput reg Q -> output Q to suppress warning
2019-12-05 Eddie Hungabc9_map.v to do `zinit' and make INIT = 1'b0
2019-12-04 Eddie HungCleanup
2019-12-04 Eddie HungAdd assertion
2019-12-04 Eddie Hungwrite_xaiger to consume abc9_init attribute for abc9_flops
2019-12-04 Eddie HungAdd abc9_init wire, attach to abc9_flop cell
2019-12-03 Eddie HungRevert "Add INIT value to abc9_control"
2019-12-03 Eddie HungUpdate ABCREV for upstream bugfix
2019-12-03 Eddie Hungtechmap abc_unmap.v before xilinx_srl -fixed
2019-12-02 Eddie HungAdd INIT value to abc9_control
2019-12-02 Eddie HungCleanup
2019-12-02 Eddie HungUse pool instead of std::set for determinism
2019-12-02 Eddie HungUse pool<> not std::set<> for determinism
2019-11-28 Eddie Hungclkpart -unpart into 'finalize'
2019-11-28 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-28 Eddie HungMove \init signal for non-port signals as long as inter...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungFix multiple driver issue
2019-11-27 Eddie HungAdd multiple driver testcase
2019-11-27 Eddie HungFix multiple driver issue
2019-11-27 Eddie HungAdd comment, use sigmap
2019-11-27 Eddie HungRevert "Fold loop"
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-27 Eddie Hungean call after abc{,9}
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungDo not replace constants with same wire
2019-11-27 Eddie HungMerge pull request #1536 from YosysHQ/eddie/xilinx_dsp_...
2019-11-27 Clifford WolfMerge pull request #1501 from YosysHQ/dave/mem_copy_attr
2019-11-27 Clifford WolfMerge pull request #1534 from YosysHQ/mwk/opt_share-fix
2019-11-27 Eddie HungMerge pull request #1535 from YosysHQ/eddie/write_xaige...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/write_xaiger...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungCleanup
2019-11-27 Eddie HungCheck for nullptr
2019-11-27 Eddie HungStray log_dump
2019-11-27 Eddie HungRevert "submod to bitty rather bussy, for bussy wires...
2019-11-27 Eddie HungPromote output wires in sigmap so that can be detected
2019-11-27 Eddie HungFix wire width
2019-11-27 Eddie HungFix submod -hidden
2019-11-27 Eddie HungAdd -hidden option to submod
2019-11-27 Eddie HungNo need for -abc9
2019-11-27 Marcin Kościelnickiopt_share: Fix handling of fine cells.
2019-11-27 Eddie Hunglatch -> box
2019-11-27 Eddie HungMerge branch 'master' into xaig_dff
2019-11-27 Eddie HungAdd citation
2019-11-27 Eddie HungCheck for either sign or zero extension for postAdd...
2019-11-27 Eddie HungRemove notes
2019-11-27 Eddie HungFold loop
2019-11-27 Eddie HungDo not sigmap keep bits inside write_xaiger
2019-11-27 Eddie Hungxaiger: do not promote output wires
2019-11-27 Eddie HungAdd testcase derived from fastfir_dynamictaps benchmark
2019-11-27 Eddie Hungxaiger: do not promote output wires
2019-11-26 Eddie HungMove 'clean' from map_luts to finalize
2019-11-26 Eddie HungFix submod -hidden
2019-11-26 Eddie Hungclkpart to use 'submod -hidden'
2019-11-26 Eddie HungAdd -hidden option to submod
2019-11-26 Eddie HungUpdate docs with bullet points
2019-11-26 Marcin Kościelnickixilinx: Add simulation models for IOBUF and OBUFT.
2019-11-26 Eddie HungMove \init from source wire to submod if output port
2019-11-26 Eddie HungAdd testcase where \init is copied
2019-11-25 Eddie HungFold loop
2019-11-25 Eddie HungDo not sigmap keep bits inside write_xaiger
2019-11-25 Eddie Hungclkpart to analyse async flops too
2019-11-25 Eddie HungFix debug
2019-11-25 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 Eddie HungSpecial abc9_clock wire to contain only clock signal
2019-11-25 Eddie Hungabc9 to contain time call
2019-11-25 Eddie Hungabc9 to no longer to clock partitioning, operate on...
2019-11-25 Eddie Hungclkpart to analyse async flops too
2019-11-25 Marcin Kościelnickiclkbufmap: Add support for inverters in clock path.
2019-11-25 Marcin Kościelnickixilinx: Use INV instead of LUT1 when applicable
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMore oopsies
2019-11-23 Eddie HungConditioning abc9 on POs not accurate due to cells
2019-11-23 Eddie HungFor abc9, run clkpart before ff_map and after abc9
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungPrint ".en=" only if there is an enable signal
2019-11-23 Eddie HungEscape IdStrings
2019-11-23 Eddie HungMore sane naming of submod
2019-11-23 Eddie HungAdd -set_attr option, -unpart to take attr name
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge branch 'xaig_dff' of github.com:YosysHQ/yosys...
2019-11-23 Eddie HungMerge pull request #1505 from YosysHQ/eddie/xaig_dff_adff
2019-11-23 Eddie HungDo not use log_signal() for empty SigSpec to prevent...
2019-11-23 Eddie HungCall submod once, more meaningful submod names, ignore...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge pull request #1520 from pietrmar/fix-1463
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungRemove redundant flatten
2019-11-23 Martin Pietrykacoolrunner2: remove spurious log_pop() call, fixes...
2019-11-23 Eddie Hungsubmod to bitty rather bussy, for bussy wires used...
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