gram.git
2020-07-03 Jean THOMASRemove remainings from TRELLIS_IO
2020-07-03 Jean THOMASCheck if YOSYS env var is set and use it as YOSYS execu...
2020-07-03 Jean THOMASUse Yosys from YoWASP
2020-07-03 Jean THOMASFix permissions for simulation script
2020-07-03 Jean THOMASAdd simulation script into SourceHut builds
2020-07-03 Jean THOMASExclude DDRDLLA from tree
2020-07-03 Jean THOMASEnsure dramsync runs at 100Mhz, sync2x at 200Mhz
2020-07-03 Jean THOMASRemove DDRDLLA
2020-07-03 Jean THOMASAdd build script for SourceHut
2020-07-03 Jean THOMASAdd tests in DFI Injector for odt and reset signals
2020-07-03 Jean THOMASCheck for additional signals in phase injector at t=0
2020-07-03 Jean THOMASAdd DFI injector test case
2020-07-03 Jean THOMASUpdate simulation gitignore
2020-07-03 Jean THOMASUpdate gram simulation documentation
2020-07-03 Jean THOMASAdd cleaning pass
2020-07-03 Jean THOMASFix autopep8 madness
2020-07-03 Jean THOMASRework CRG simulation
2020-07-03 Jean THOMASExternalize CRG into its own file
2020-07-03 Jean THOMASAdd devel doc
2020-07-03 Jean THOMASAdd test for Refresher
2020-07-03 Jean THOMASRefactor generic_test execution
2020-07-03 Jean THOMASUse spaces for indentation
2020-07-03 Jean THOMASAdd tests for core/refresher.py
2020-07-03 Jean THOMASRemoving reset=0 attribute as it is already the default...
2020-07-02 Jean THOMASUse reset signal from dramsync instead of sync
2020-07-02 Jean THOMASMake RefreshPostponer more similar to LiteDRAM's
2020-07-02 Jean THOMASFix RefreshPostponer output stuck to 1
2020-07-02 Jean THOMASFlatten specific parts of the designs
2020-07-02 Jean THOMASAdd missing command issue strobe for ZQ calibration
2020-07-02 Jean THOMASRemove PyYAML dependency
2020-07-02 Jean THOMASFix register addresses, add missing command_issue strobe
2020-07-02 Jean THOMASSet names to prevent CSR/DomainRenamer incompatibility
2020-07-02 Jean THOMASAdd DDRDLLA patch
2020-07-01 Jean THOMASFix merge
2020-07-01 Jean THOMASRework indentation and add Wishbone tests
2020-07-01 Jean THOMASAdd Wishbone interaction code
2020-07-01 Jean THOMASAdd Wishbone interaction code
2020-07-01 Jean THOMASFix Iverilog simulation
2020-07-01 Jean THOMASGenerate ilang file
2020-06-30 Jean THOMASBuild nMigen gateware in a specific folder
2020-06-30 Jean THOMASRemove LED code in CRG
2020-06-30 Jean THOMASRemove Minerva dependency
2020-06-30 Jean THOMASApplying #9044c10 changes in LiteDRAM (phy/ecp5ddrphy...
2020-06-29 Jean THOMASDefine simulation time as a parameter
2020-06-29 Jean THOMASDefine PLL's PHASELOADREG input
2020-06-29 Jean THOMASUse -n option in vvp to enable CTRL+C
2020-06-29 Jean THOMASFix PLL instanciation code for CRG simulation
2020-06-29 Jean THOMASDump whole module
2020-06-29 Jean THOMASFix DQSBUFM floating DYNDELAY
2020-06-29 Jean THOMASSet DRAM's CK_N to low
2020-06-29 Jean THOMASFix autopep8 madness
2020-06-29 Jean THOMASUse BB instead of TRELLIS_IO
2020-06-29 Jean THOMASFix CRG, revert to resetful sync domain
2020-06-29 Jean THOMASSet UART RX to 1'b1
2020-06-29 Jean THOMASAdd -Wall to simulations
2020-06-26 Jean THOMASAdd testbench for SoC simulation
2020-06-26 Jean THOMASUse FST instead of VCD
2020-06-26 Jean THOMASExclude .fst files
2020-06-26 Jean THOMASAdd DDRSoC simulation
2020-06-26 Jean THOMASAdd gitignore for simulation folder
2020-06-26 Jean THOMASFix PLL code
2020-06-26 Jean THOMASAdd DRAM model
2020-06-25 Jean THOMASFix typo
2020-06-25 Jean THOMASAdd simulation code
2020-06-25 Jean THOMASAdd README.md for gram tests
2020-06-25 Jean THOMASAdd rddata_en, wrdata_mask tests
2020-06-25 Jean THOMASAdd wrdata, wrdata_en tests to Phase Injector unit...
2020-06-25 Jean THOMASFix R/W permissions to the bare minimum
2020-06-25 Jean THOMASSet UART bridge SEL signals to 0xF
2020-06-25 Jean THOMASAdd Wishbone read/write helpers
2020-06-25 Jean THOMASUse constants for CSR addresses
2020-06-25 Jean THOMASAdd bank address test
2020-06-25 Jean THOMASFix DFII testing, test address set
2020-06-24 Jean THOMASAdd buggy test for DFII
2020-06-24 Jean THOMASFix CSR issue in PhaseInjector (r_data used for reading...
2020-06-24 Jean THOMASFix CSR issue in DFII (r_data used for reading host...
2020-06-24 Jean THOMASSimply arbiter when there is only 1 request to arbitrate
2020-06-24 Jean THOMASEnsure we have at least one master
2020-06-23 Jean THOMASOnly declare wants_zqcs signal if needed
2020-06-23 Jean THOMASSimplify connections from refreshers to IOs (not FSM...
2020-06-23 Jean THOMASRefactor test code
2020-06-23 Jean THOMASFix DFII bitfield constants
2020-06-23 Jean THOMASFix public libgram header
2020-06-23 Jean THOMASCompile libgram as C99 code
2020-06-23 Jean THOMASFix typo in GramWidth enum declaration
2020-06-23 Jean THOMASFix ZQCSExecuter (set a signal to the proper size)...
2020-06-23 Jean THOMASRefresher: fix a address size (fixes #14)
2020-06-22 Jean THOMASRemove shadowing statement
2020-06-22 Jean THOMASReplace bits_for with range
2020-06-22 Jean THOMASRemove code for hybrid formal proof, unused
2020-06-22 Jean THOMASRollback to the ECP5 P/N used in ECPIX-5
2020-06-22 Jean THOMASFix pinout
2020-06-22 Jean THOMASUse TRELLIS_IO instead of BB in ECP5 PHY
2020-06-19 Jean THOMASUpdate memtest code in libgram
2020-06-19 Jean THOMASRemove tests from gram.compat
2020-06-19 Jean THOMASMove tests to a dedicated folder
2020-06-18 Jean THOMASAdd unit tests for delayed_enter
2020-06-18 Jean THOMASAdd test case for delayed_enter
2020-06-18 Jean THOMASUse BB instance for bidirectionnal IOs
2020-06-17 Jean THOMASRemove lambdasoc dependency from UARTBridge
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