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yosys.git
2016-07-27 Clifford WolfAdded "read_verilog -dump_rtlil" commit | commitdiff | tree
2016-07-25 Clifford WolfRenamed AbstractCellEdgesDatabase::add_cell() to add_ed... commit | commitdiff | tree
2016-07-25 Clifford WolfFixed a verilog parser memory leak commit | commitdiff | tree
2016-07-25 Clifford WolfFixed parsing of empty positional cell ports commit | commitdiff | tree
2016-07-24 Clifford WolfImprovements in CellEdgesDatabase commit | commitdiff | tree
2016-07-24 Clifford WolfAdded CellEdgesDatabase API commit | commitdiff | tree
2016-07-24 Clifford WolfMoved SatHelper::setup_init() code to SatHelper::setup() commit | commitdiff | tree
2016-07-23 Clifford WolfAdded $initstate support to "sat" command commit | commitdiff | tree
2016-07-23 Clifford WolfNo tristate warning message for "read_verilog -lib" commit | commitdiff | tree
2016-07-22 Clifford WolfAdded satgen initstate support commit | commitdiff | tree
2016-07-21 Clifford WolfUsing $initstate in "initial assume" and "initial assert" commit | commitdiff | tree
2016-07-21 Clifford WolfAdded $initstate cell type and vlog function commit | commitdiff | tree
2016-07-21 Clifford WolfAfter reading the SV spec, using non-standard predict... commit | commitdiff | tree
2016-07-13 Clifford WolfAdded basic support for $expect cells commit | commitdiff | tree
2016-07-13 Clifford WolfAdded examples/smtbmc commit | commitdiff | tree
2016-07-13 Clifford WolfMerge pull request #191 from whitequark/json-module... commit | commitdiff | tree
2016-07-13 Clifford WolfMerge pull request #193 from azonenberg/master commit | commitdiff | tree
2016-07-12 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys commit | commitdiff | tree
2016-07-12 Clifford WolfMinor bugfix in FSM reset state detection commit | commitdiff | tree
2016-07-12 whitequarkwrite_json: also write module attributes. commit | commitdiff | tree
2016-07-12 Andrew ZonenbergAdded GP_DAC cell commit | commitdiff | tree
2016-07-12 Andrew ZonenbergRemoved VOUT port of GP_BANDGAP commit | commitdiff | tree
2016-07-12 Andrew ZonenbergRemoved splitnets in prep for new gp4par parser commit | commitdiff | tree
2016-07-11 Clifford WolfYosys-smtbmc: Support for hierarchical VCD dumping commit | commitdiff | tree
2016-07-11 Clifford WolfMoved smt2 yosys info parsing from smtbmc.py to smtio.py commit | commitdiff | tree
2016-07-11 Clifford WolfAdded "prep -auto-top" and "synth -auto-top" commit | commitdiff | tree
2016-07-10 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys commit | commitdiff | tree
2016-07-10 Clifford WolfMerge pull request #189 from whitequark/master commit | commitdiff | tree
2016-07-10 Clifford WolfSupport for hierarchical designs in smt2 back-end commit | commitdiff | tree
2016-07-10 whitequarkgreenpak4: add GP_COUNT{8,14}_ADV cells. commit | commitdiff | tree
2016-07-09 Clifford WolfFurther improved fsm_detect output, attempt to detect... commit | commitdiff | tree
2016-07-09 Clifford WolfAdded printing of some warning messages to fsm_detect commit | commitdiff | tree
2016-07-08 Clifford WolfAdded warning about adding fsm_encoding attributes... commit | commitdiff | tree
2016-07-08 Clifford WolfMinor fixes in ice40_ff* passes for sloppy SB_DFF insta... commit | commitdiff | tree
2016-07-08 Clifford WolfFixed mem assignment in left-hand-side concatenation commit | commitdiff | tree
2016-07-08 Clifford WolfMerge branch 'eddiehung-vtr' commit | commitdiff | tree
2016-07-08 Clifford WolfRestored blif "-true - .." behavior, use "-true + ... commit | commitdiff | tree
2016-07-08 Clifford WolfIn BLIF, a .names without entries already always outputs 0 commit | commitdiff | tree
2016-07-08 Clifford WolfUndo eddiehung-vtr Makefile changes commit | commitdiff | tree
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com... commit | commitdiff | tree
2016-07-02 Clifford WolfFixed autotest.sh handling of `timescale commit | commitdiff | tree
2016-07-01 Clifford WolfMerge branch 'assert-limit' commit | commitdiff | tree
2016-07-01 Clifford WolfReplaced "select -assert-limit" with -assert-max and... commit | commitdiff | tree
2016-07-01 eshellkoAdded 'assert-limit' option for 'select' command commit | commitdiff | tree
2016-06-30 Clifford WolfImproved ice40_ffinit error reporting commit | commitdiff | tree
2016-06-21 Clifford WolfMerge pull request #181 from rubund/input_logic_allowed commit | commitdiff | tree
2016-06-20 Ruben UndheimAllow defining input ports as "input logic" in SystemVe... commit | commitdiff | tree
2016-06-19 Clifford WolfBugfix in "abc -script" handling commit | commitdiff | tree
2016-06-19 Clifford WolfMerge branch 'sv_packages' of https://github.com/rubund... commit | commitdiff | tree
2016-06-19 Clifford WolfAdded "deminout" commit | commitdiff | tree
2016-06-18 Ruben UndheimA few modifications after pull request comments commit | commitdiff | tree
2016-06-18 Clifford WolfAdded "read_blif -sop" commit | commitdiff | tree
2016-06-18 Clifford WolfAdded $sop support to BLIF back-end commit | commitdiff | tree
2016-06-18 Ruben UndheimAdded support for SystemVerilog packages with localpara... commit | commitdiff | tree
2016-06-17 Clifford WolfAdded "dc2" to default ABC scripts commit | commitdiff | tree
2016-06-17 Clifford WolfFixed init issue in mem2reg_test2 test case commit | commitdiff | tree
2016-06-17 Clifford WolfAdded "abc -I <num> -P <num>" commit | commitdiff | tree
2016-06-17 Clifford WolfAdded $sop SAT model commit | commitdiff | tree
2016-06-17 Clifford WolfImproved support for $sop cells commit | commitdiff | tree
2016-06-17 Clifford WolfAdded $sop cell type and "abc -sop" commit | commitdiff | tree
2016-06-17 Clifford WolfUpdated ABC to hg rev b5df6e2b76f0 commit | commitdiff | tree
2016-06-09 Clifford WolfAdded "nlutmap -assert" commit | commitdiff | tree
2016-06-08 Clifford WolfDo not run "wreduce" in "prep -ifx" commit | commitdiff | tree
2016-06-06 Clifford WolfAdded "proc_mux -ifx" commit | commitdiff | tree
2016-06-03 Clifford WolfAdded "setundef -init" commit | commitdiff | tree
2016-06-02 Clifford WolfFix all undef-muxes in dlatch input cone commit | commitdiff | tree
2016-06-01 Clifford WolfAvoid creating undef-muxes when inferring latches in... commit | commitdiff | tree
2016-05-29 Clifford WolfAdded opt_expr support for div/mod by power-of-two commit | commitdiff | tree
2016-05-27 Clifford WolfFixed procedural assignments to non-unique lvalues... commit | commitdiff | tree
2016-05-27 Clifford WolfFixed access-after-delete bug in mem2reg code commit | commitdiff | tree
2016-05-27 Clifford Wolffixed typos in error messages commit | commitdiff | tree
2016-05-27 Clifford WolfFixed "scc" for cells that have feedback singals _and_... commit | commitdiff | tree
2016-05-22 Clifford WolfMerge pull request #172 from zeldin/deterministic_hierarchy commit | commitdiff | tree
2016-05-22 Marcus ComstedtMade the expansion order of hierarchy deterministic commit | commitdiff | tree
2016-05-20 Clifford WolfSome fixes in tests/asicworld/*_tb.v commit | commitdiff | tree
2016-05-20 Clifford WolfImprovements and fixes in autotest.sh script and test_a... commit | commitdiff | tree
2016-05-20 Clifford WolfMerge branch 'master' of https://github.com/Kmanfi... commit | commitdiff | tree
2016-05-20 Clifford WolfAlso escape "=" in spice output commit | commitdiff | tree
2016-05-20 Clifford WolfSmall improvements in Verilog front-end docs commit | commitdiff | tree
2016-05-19 Kaj TuomiClose opened dump file. commit | commitdiff | tree
2016-05-19 Kaj TuomiFix for Modelsim transcript line warp issue #164 commit | commitdiff | tree
2016-05-14 Clifford WolfDon't sign-extend memory bram initialization data commit | commitdiff | tree
2016-05-14 Clifford WolfAdded missing "#define HASHLIB_H" commit | commitdiff | tree
2016-05-14 Clifford WolfMinor presentation fixes commit | commitdiff | tree
2016-05-11 Clifford WolfUpdated min GCC requirement to GCC 4.8 commit | commitdiff | tree
2016-05-09 Clifford WolfAdded manual download link to README commit | commitdiff | tree
2016-05-08 Clifford WolfInclude <cmath> in yosys.h commit | commitdiff | tree
2016-05-08 Clifford WolfMerge pull request #162 from azonenberg/master commit | commitdiff | tree
2016-05-08 Andrew ZonenbergAdded GP_DELAY cell commit | commitdiff | tree
2016-05-08 Andrew ZonenbergFixed typo in port name commit | commitdiff | tree
2016-05-08 Andrew ZonenbergFixed extra semicolon commit | commitdiff | tree
2016-05-08 Andrew ZonenbergFixed typo in parameter name commit | commitdiff | tree
2016-05-08 Andrew ZonenbergAdded simulation timescale declaration commit | commitdiff | tree
2016-05-07 Clifford WolfFixes for MXE build commit | commitdiff | tree
2016-05-07 Clifford WolfAdded support for "keep" attribute to shregmap commit | commitdiff | tree
2016-05-06 Clifford WolfAdded synth_ice40 support for latches via logic loops commit | commitdiff | tree
2016-05-06 Clifford WolfAdded "write_blif -noalias" commit | commitdiff | tree
2016-05-06 Clifford WolfFixed ice40_opt lut unmapping, added "ice40_opt -unlut" commit | commitdiff | tree
2016-05-06 Clifford WolfFixed preservation of important attributes in techmap commit | commitdiff | tree
2016-05-05 Clifford WolfMerge pull request #159 from azonenberg/master commit | commitdiff | tree
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