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gem5.git
2012-08-21
Andreas Hansson
CPU: Remove overloaded function_trace_start parameter
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2012-08-21
Andreas Hansson
PacketQueue: Allow queuing in the same tick as desired...
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2012-08-21
Andreas Hansson
EventManager: Remove test for NULL pointer in constructor
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2012-08-21
Andreas Hansson
Clock: Make Tick unsigned and remove UTick
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2012-08-21
Andreas Hansson
Clock: Move the clock and related functions to ClockedO...
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2012-08-21
Andreas Hansson
Checkpoint: Fix broken checkpointing functionality
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2012-08-19
Nilay Vaish
Ruby Banked Array: add copyrights
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2012-08-17
Jason Power
Ruby: Add RubySystem parameter to MemoryControl
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2012-08-17
Nilay Vaish
Alpha System: override startup(), instead of loadState()
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2012-08-15
Anthony Gutierrez
O3,ARM: fix some problems with drain/switchout function...
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2012-08-15
Anthony Gutierrez
configs: add option for repeatedly switching back-and...
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2012-08-15
Ali Saidi
stats: Update stats for syscall emulation Linux kernel...
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2012-08-15
Ali Saidi
sysemul: bump all linux versions of for syscal emulatio...
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2012-08-10
Jason Power
Ruby: Clean up topology changes
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2012-08-08
Nilay Vaish
System: set kernel to null, if unspecified.
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2012-08-07
Marc Orr
syscall emulation: Enabled getrlimit and getrusage...
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2012-08-06
Steve Reinhardt
SETranslatingPortProxy: fix bug in tryReadString()
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2012-08-06
Steve Reinhardt
process: add progName() virtual function
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2012-08-06
Steve Reinhardt
syscall_emul: clean up open() code a bit.
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2012-08-06
Steve Reinhardt
str: add an overloaded startswith() utility method
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2012-08-06
Marc Orr
syscall emulation: Clean up ioctl handling, and impleme...
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2012-08-06
Nilay Vaish
Simulation.py: move code related to checkpointing to...
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2012-08-06
Nilay Vaish
Config: change how cpu class is set
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2012-08-01
Jason Power
Ruby NetDest: add assert for bad element in netdest
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2012-07-30
Ali Saidi
stats: revert pc-simple-timing-ruby-MESI_CMP_directory...
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2012-07-28
Ali Saidi
stats: fix some miss-committed changes from the icache...
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2012-07-27
Nathanael Premillieu
util: Fix issues with style checker.
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2012-07-27
Ali Saidi
stats: update stats for icache change not allowing...
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2012-07-27
Anthony Gutierrez
dma: remove unused variable
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2012-07-27
Anthony Gutierrez
checker: make checker cpu id match its host's cpu id
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2012-07-27
Anthony Gutierrez
cache: don't allow dirty data in the i-cache
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2012-07-27
Anthony Gutierrez
ARM: fix value of MISCREG_CTR returned by readMiscReg()
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2012-07-23
Andreas Hansson
Config: Use clock option in se/fs script and pass to...
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2012-07-23
Andreas Hansson
Bridge: Use EventWrapper instead of Event subclass...
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2012-07-23
Steve Reinhardt
test: Update eio ref outputs due to recent changes
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2012-07-23
Steve Reinhardt
test: Restore eio ref files clobbered in rev 8800b05e1cb3.
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2012-07-23
Nilay Vaish
Regression: Update stats due to changes to x86 cpuid...
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2012-07-23
Nilay Vaish
X86 CPUID: Return false if unknown processor family
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2012-07-21
Andreas Hansson
Regression: Fix topologies path in failing pc-simple...
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2012-07-19
Steve Reinhardt
Added tag stable_2012_06_28 for changeset f75ee4849c40
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2012-07-19
Steve Reinhardt
Added tag stable_2012_02_02 for changeset 549b72de8f72
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2012-07-12
Andreas Hansson
Mem: Make SimpleMemory single ported
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2012-07-12
Andreas Hansson
scons: Add LIBRARY_PATH from the user environment to...
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2012-07-12
Nilay Vaish
Regression: update ruby.stats file
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2012-07-12
Nilay Vaish
Ruby: remove config information from ruby.stats
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2012-07-12
Nilay Vaish
Ruby: remove some unused stuff from SLICC files
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2012-07-11
Brad Beckmann
x86: added page size in bytes tlb entry function
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2012-07-11
Brad Beckmann
ruby: improved DRAM reset comment
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2012-07-11
Brad Beckmann
regress: ruby stat additions and config changes
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2012-07-11
Marc Orr
syscall emulation: Add the futex system call.
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2012-07-11
Brad Beckmann
x86: logSize and lruSeq are now optional ckpt params
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2012-07-11
Steve Reinhardt
Add hook to call map() on Process from python.
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2012-07-11
Brad Beckmann
# User Brad Beckmann <Brad.Beckmann@amd.com>
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2012-07-11
Brad Beckmann
ruby: remove the cpu assumptions for the random tester
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2012-07-11
Brad Beckmann
# User Brad Beckmann <Brad.Beckmann@amd.com>
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2012-07-11
Brad Beckmann
imported patch jason/slicc-external-structure-fix
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2012-07-11
Brad Beckmann
ruby: banked cache array resource model
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2012-07-11
Joel Hestness
ruby: tag and data cache access support
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2012-07-11
Nuwan Jayasena
ruby: adds reset function to Ruby memory controllers
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2012-07-11
Nuwan Jayasena
ruby: memory controllers now inherit from an abstract...
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2012-07-11
Brad Beckmann
cpu: added assertions to ensure the correct proxies...
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2012-07-11
Brad Beckmann
ruby: changes how Topologies are created
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2012-07-09
Andreas Hansson
EventManager: Rename queue accessor and remove cast...
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2012-07-09
Andreas Hansson
Mem: Make members relating to range and size constant
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2012-07-09
Andreas Hansson
Port: Hide the queue implementation in SimpleTimingPort
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2012-07-09
Andreas Hansson
Stats: Updates due to bus changes
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2012-07-09
Andreas Hansson
Port: Align port names in C++ and Python
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2012-07-09
Andreas Hansson
Bus: Make the default bus width 8 bytes instead of 64
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2012-07-09
Andreas Hansson
Bus: Split the bus into separate request/response layers
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2012-07-09
Andreas Hansson
Bus: Add a notion of layers to the buses
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2012-07-09
Andreas Hansson
Bus: Replace tickNextIdle and inRetry with a state...
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2012-07-09
Andreas Hansson
Port: Make getAddrRanges const
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2012-07-09
Andreas Hansson
Port: Add getAddrRanges to master port (asking slave...
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2012-07-09
Andreas Hansson
Port: Add isSnooping to slave port (asking master port)
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2012-07-09
Andreas Hansson
Port: Move retry from port base class to Master/SlavePort
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2012-07-09
Andreas Hansson
Fix: Address a few benign memory leaks
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2012-07-02
Andreas Hansson
gcc: Fix warnings for gcc 4.7 and clang 3.1
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2012-06-29
Lena Olson
Cache: Fix the LRU policy for classic memory hierarchy
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2012-06-29
Uri Wiener
Bus: enable non/coherent buses sub-classes
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2012-06-29
Dam Sunwoo
Mem: fix master id assertion in cache_impl.hh
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2012-06-29
Matt Evans
Style: Make style.py's invalid warning print which...
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2012-06-29
Matt Evans
Mem: Fix a livelock resulting in LLSC/locked memory...
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2012-06-29
Ali Saidi
Stats: Update stats for RAS and LRU fixes.
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2012-06-29
Nathanael Premillieu
O3: Track if the RAS has been pushed or not to pop...
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2012-06-29
Ali Saidi
ARM: Fix identification of one RAS pop instruction.
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2012-06-29
Ali Saidi
Cache: Only invalidate a line in the cache when an...
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2012-06-29
Ali Saidi
ARM: Update version of linux we claim to be to 3.0.0.
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2012-06-29
Ali Saidi
ARM: Fix issue with predicted next pc being wrong becau...
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2012-06-27
Ali Saidi
ARM: Fix address range issue with VExpress EMM
stable_2012_06_28
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2012-06-20
Andreas Hansson
swig: Use SWIG from environment when determining version
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2012-06-18
Andreas Hansson
Build: Point to the appropriate tcmalloc package
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2012-06-11
Anthony Gutierrez
configs: add run scripts for ics/gb versions of android...
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2012-06-11
Anthony Gutierrez
ARM: implement the ProcessInfo methods
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2012-06-11
Ali Saidi
scons: Make compiler version error more verbose and...
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2012-06-11
Marc Orr
Regression: Fix some bugs in simple-timing-mp-ruby.py.
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2012-06-08
Andreas Hansson
Timing CPU: Remove a redundant port pointer
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2012-06-08
Andreas Hansson
Power: Fix MaxMiscDestRegs which was set to zero
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2012-06-07
Nilay Vaish
X86 TLB: Add a missing = sign
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2012-06-07
Ali Saidi
mem: Delay deleting of incoming packets by one call.
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2012-06-07
Jayneel Gandhi
X86 TLB: Fix for gcc 4.4.3
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