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yosys.git
2020-02-27
Eddie Hung
synth_ecp5: use +/abc9_model.v
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2020-02-27
Eddie Hung
Update xilinx for ABC9
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2020-02-27
Eddie Hung
Create +/abc9_model.v for $__ABC9_{DELAY,FF_}
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2020-02-27
Eddie Hung
abc9_ops: output LUT area
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2020-02-27
Eddie Hung
ecp5: remove small LUT entries
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2020-02-27
Eddie Hung
abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto...
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2020-02-27
Eddie Hung
Fix commented out specify statement
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2020-02-27
Eddie Hung
xilinx: improve specify functionality
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2020-02-27
Eddie Hung
ecp5: deprecate abc9_{arrival,required} and *.{lut...
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2020-02-27
Eddie Hung
xilinx: use specify blocks in place of abc9_{arrival...
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2020-02-27
Eddie Hung
Auto-generate .box/.lut files from specify blocks
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2020-02-27
Eddie Hung
abc9_ops: assert on $specify2 properties
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2020-02-27
Eddie Hung
abc9_ops: -prep_box, to be called once
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2020-02-27
Eddie Hung
abc9_ops: -prep_lut and -write_lut to auto-generate...
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2020-02-27
Claire Wolf
Merge pull request #1709 from rqou/coolrunner2_counter
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2020-02-27
Claire Wolf
Merge pull request #1708 from rqou/coolrunner2-buf-fix
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2020-02-27
Piotr Binkowski
xilinx: mark IOBUFDSE3 IOB pin as external
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2020-02-26
Miodrag Milanović
Merge pull request #1705 from YosysHQ/logger_pass
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2020-02-26
Miodrag Milanovic
Remove tests for now
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2020-02-23
Miodrag Milanovic
Add tests for logger pass
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2020-02-23
Miodrag Milanovic
Remove duplicate warning detection
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2020-02-23
Miodrag Milanovic
Fix line endings
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2020-02-22
Eddie Hung
Merge pull request #1715 from boqwxp/master
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2020-02-22
Miodrag Milanovic
Update explanation for expect-no-warnings
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2020-02-22
Miodrag Milanovic
Handle expect no warnings together with expected
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2020-02-22
Miodrag Milanovic
Check other regex parameters
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2020-02-22
Alberto Gonzalez
Closes #1714. Fix make failure when NDEBUG=1.
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2020-02-21
Eddie Hung
Merge pull request #1703 from YosysHQ/eddie/specify_improve
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2020-02-20
Claire Wolf
Merge pull request #1642 from jjj11x/jjj11x/sv-enum
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2020-02-20
Miodrag Milanovic
check for regex errors
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2020-02-19
Eddie Hung
verilog: add support for more delays than just rise...
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2020-02-19
Eddie Hung
clean: ignore specify-s inside cells when determining...
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2020-02-17
Miodrag Milanovic
Prevent double error message
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2020-02-17
Miodrag Milanovic
Option to expect no warnings
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2020-02-17
Miodrag Milanovic
Add to changelog
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2020-02-17
Miodrag Milanovic
No new error if already failing
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2020-02-17
R. Ou
coolrunner2: Use extract_counter to optimize counters
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2020-02-17
R. Ou
extract_counter: Implement extracting up counters
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2020-02-17
R. Ou
extract_counter: Add support for inverted clock enable
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2020-02-17
R. Ou
extract_counter: Fix clock enable
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2020-02-17
R. Ou
extract_counter: Fix outputting count to module port
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2020-02-17
R. Ou
extract_counter: Allow forbidding async reset
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2020-02-17
R. Ou
extract_counter: Refactor out extraction settings into...
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2020-02-17
Jeff Wang
update documentation for enums and typedefs
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2020-02-17
Jeff Wang
remove unnecessary blank line
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2020-02-17
Jeff Wang
add attributes for enumerated values in ilang
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2020-02-17
Jeff Wang
separate out enum_item/param implementation when they...
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2020-02-17
R. Ou
coolrunner2: Separate and improve buffer cell insertion...
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2020-02-15
Marcin Kościelnicki
tests/aiger: Add missing .gitignore
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2020-02-15
Tim 'mithro...
show: Add -nobg argument.
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2020-02-15
Miodrag Milanović
Merge pull request #1706 from YosysHQ/mmicko/remove_exe...
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2020-02-15
Miodrag Milanovic
Remove executable flag from files
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2020-02-15
Miodrag Milanović
Add comment for macOS dependency install
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2020-02-15
Eddie Hung
Revert "abc9: fix abc9_arrival for flops"
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2020-02-14
Miodrag Milanovic
remove whitespace
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2020-02-14
Miodrag Milanovic
Add expect option to logger command
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2020-02-14
Miodrag Milanović
Merge pull request #1701 from nakengelhardt/rpc-test
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2020-02-14
Eddie Hung
verilog: ignore ranges too without -specify
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2020-02-14
Eddie Hung
Merge pull request #1700 from YosysHQ/eddie/abc9_fixes
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2020-02-14
Eddie Hung
Merge pull request #1699 from YosysHQ/eddie/fix_iopad_init
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2020-02-13
Eddie Hung
Fine tune #1699 tests
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2020-02-13
Eddie Hung
iopadmap: fixes as suggested by @mwkmwkmwk
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2020-02-13
Eddie Hung
verilog: improve specify support when not in -specify...
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2020-02-13
Eddie Hung
verilog: ignore '&&&' when not in -specify mode
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2020-02-13
Eddie Hung
specify: system timing checks to accept min:typ:max...
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2020-02-13
Eddie Hung
verilog: fix $specify3 check
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2020-02-13
Eddie Hung
write_xaiger: default value for abc9_init
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2020-02-13
Eddie Hung
abc9: fix abc9_arrival for flops
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2020-02-13
Eddie Hung
abc9: deprecate abc9_ff.init wire for (* abc9_init...
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2020-02-13
Eddie Hung
iopadmap: move \init attributes from outpad output...
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2020-02-13
N. Engelhardt
make rpc frontend unix socket test less fragile
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2020-02-13
Claire Wolf
Merge pull request #1694 from rqou/json_compat_fix
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2020-02-13
Miodrag Milanovic
Add new logger pass
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2020-02-13
N. Engelhardt
Merge pull request #1679 from thasti/delay-parsing
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2020-02-10
Eddie Hung
abc9: cleanup
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2020-02-10
Eddie Hung
Merge pull request #1670 from rodrigomelo9/master
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2020-02-10
N. Engelhardt
Merge pull request #1669 from thasti/pyosys-attrs
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2020-02-09
whitequark
Merge pull request #1695 from whitequark/manual-explain...
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2020-02-09
whitequark
manual: explain RTLIL::Wire::{upto,offset}.
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2020-02-09
R. Ou
json: Change compat mode to directly emit ints <= 32...
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2020-02-07
Eddie Hung
Remove unnecessary comma
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2020-02-07
Eddie Hung
Merge pull request #1687 from YosysHQ/eddie/fix_ystests
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2020-02-07
Eddie Hung
techmap: fix shiftx2mux decomposition
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2020-02-07
Eddie Hung
Fix misc.abc9.abc9_abc9_luts
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2020-02-07
Marcin Kościelnicki
xilinx: Add support for LUT RAM on LUT4-based devices.
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2020-02-07
Marcin Kościelnicki
xilinx: Initial support for LUT4 devices.
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2020-02-07
Eddie Hung
Merge pull request #1685 from dh73/gowin
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2020-02-07
whitequark
Merge pull request #1683 from whitequark/write_verilog...
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2020-02-07
Marcin Kościelnicki
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07
Marcin Kościelnicki
xilinx: Add support for Spartan 3A DSP block RAMs.
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2020-02-06
Eddie Hung
Merge pull request #1684 from YosysHQ/eddie/xilinx_arit...
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2020-02-06
Diego H
Removing cells_sim.v from bram techmap pass
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2020-02-06
Eddie Hung
Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk
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2020-02-06
Eddie Hung
Fix/cleanup +/xilinx/arith_map.v
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2020-02-06
Marcin Kościelnicki
edif: more resilience to mismatched port connection...
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2020-02-06
whitequark
write_verilog: dump $mem cell attributes.
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2020-02-06
Rodrigo Alejandro...
Added 'set -e' into tests/memfile/run-test.sh
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2020-02-06
Rodrigo Alejandro...
Modified $readmem[hb] to use '\' or '/' according the OS
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2020-02-06
Eddie Hung
Merge pull request #1682 from YosysHQ/eddie/opt_after_t...
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2020-02-06
Eddie Hung
synth_*: call 'opt -fast' after 'techmap'
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