yosys.git
2019-02-21 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-02-21 Eddie Hungtests/simple to also do LUT synth
2019-02-21 Eddie HungWorking simple_abc9 tests
2019-02-21 Eddie Hungabc9 to only disconnect output ports of AND and NOT...
2019-02-21 Eddie Hungwrite_xaiger to use original bit for co, not sigmap...
2019-02-21 Eddie HungAdd abc9.v testcase to simple_abc9
2019-02-21 Clifford WolfHotfix for 4c82ddf
2019-02-21 Clifford WolfMerge pull request #822 from litghost/expand_setundef
2019-02-21 Keith RothmanAdd -params mode to force undef parameters in selected...
2019-02-21 Clifford WolfMerge pull request #818 from YosysHQ/clifford/dffsrfix
2019-02-21 Clifford WolfMerge pull request #786 from YosysHQ/pmgen
2019-02-21 Clifford WolfFix typo in passes/pmgen/README.md
2019-02-21 Clifford WolfMerge pull request #821 from eddiehung/dff_init
2019-02-21 Eddie HungMerge branch 'clifford/dffsrfix' of https://github...
2019-02-21 Eddie HungRevert "Add -B option to autotest.sh to append to backe...
2019-02-21 Clifford WolfFix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_...
2019-02-21 Clifford WolfBugfix in ice40_dsp
2019-02-21 Eddie HungABC -> ABC9
2019-02-21 Eddie Hungabc9 to disconnect mapped_mods POs correctly, and do...
2019-02-21 Eddie Hungread_aiger to not do -purge for clean
2019-02-21 Eddie HungMerge pull request #817 from eddiehung/dff_init
2019-02-21 Eddie Hunglut/not/and suffix to be ${lut,not,and}
2019-02-21 Eddie Hungsimple_abc9 tests to now preserve memories
2019-02-21 Eddie Hungread_aiger to also rename 0 index lut when wideports
2019-02-21 Eddie HungRemove swap file
2019-02-20 Eddie HungRemove simple_defparam tests
2019-02-20 Eddie Hungwrite_aiger: fix CI/CO and symbols
2019-02-20 Eddie HungMove tests/techmap/abc9 to simple_abc9
2019-02-20 Eddie HungAdd tests/simple_abc9
2019-02-20 Eddie Hungabc9 to cope with multiple modules
2019-02-20 Eddie Hungabc9 to use & syntax for -fast, and name fixes
2019-02-20 Eddie Hungread_aiger: new naming fixes
2019-02-20 Eddie Hungread_aiger to name wires with internal name, less likel...
2019-02-20 Eddie Hungwrite_xaiger to not write latches, CO/PO fixes
2019-02-20 Eddie Hungsynth to take -abc9 argument
2019-02-20 Clifford WolfAdd ice40 test_dsp_map test case generator
2019-02-20 Clifford WolfAdd "synth_ice40 -dsp"
2019-02-20 Clifford WolfAdd FF support to wreduce
2019-02-20 Clifford WolfImprove iCE40 SB_MAC16 model
2019-02-20 Clifford WolfDetect and reject cases that do not map well to iCE40...
2019-02-20 Eddie Hungabc9 to cope with indexed wires when creating $lut...
2019-02-19 Eddie HungAdd a quick abc9 test
2019-02-19 Eddie HungSame for ascii AIGERs too
2019-02-19 Eddie Hungread_aiger to cope with non-unique POs
2019-02-19 Eddie HungMerge branch 'master' into xaig
2019-02-19 Eddie HungMerge pull request #805 from eddiehung/dff_init
2019-02-19 Eddie Hungabc9 to replace $_NOT_ with $lut
2019-02-19 Eddie Hungread_aiger to create sane $lut names, and rename when...
2019-02-19 Eddie HungAdd comment
2019-02-19 Eddie HungGet rid of boost dep, fix the FIXMEs for Win32?
2019-02-19 Clifford WolfAdd first draft of functional SB_MAC16 model
2019-02-17 Eddie HungInstead of INIT param on cells, use initial statement...
2019-02-17 Eddie HungRevert "Add INIT parameter to all ff/latch cells"
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 Clifford WolfAdd actual DSP inference to ice40_dsp pass
2019-02-17 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-02-17 Clifford WolfMerge pull request #811 from ucb-bar/firrtlfixes
2019-02-17 Eddie HungGet rid of debugging stuff in abc9
2019-02-17 Eddie HungIn read_xaiger, do not construct ConstEval for every LUT
2019-02-17 Eddie HungCleanup
2019-02-17 Eddie Hungread_aiger to ignore output = input of same wire; also...
2019-02-17 Eddie HungCleanup
2019-02-17 Eddie Hungwrite_xaiger to support non-bit cell connections, and...
2019-02-17 Eddie Hungabc9 to write_aiger with -O option, and ignore dummy...
2019-02-17 Eddie Hungwrite_aiger -O to write dummy output as __dummy_o__
2019-02-16 Eddie Hungabc9 to handle comb loops, cope with constant outputs...
2019-02-16 Eddie Hungread_aiger to disable log_debug
2019-02-16 Eddie Hungexpose command to not skip 'internal' wires beginning...
2019-02-16 Eddie Hungread_xaiger() to use f.read() not readsome()
2019-02-16 Eddie Hungabc9 to cope with non-wideports, count cells properly
2019-02-16 Eddie HungTidy up write_xaiger
2019-02-16 Eddie Hungwrite_aiger() to perform CI/CO post-processing and...
2019-02-16 Eddie Hungread_aiger() to cope with constant outputs, mixed widep...
2019-02-15 Eddie HungMove lookup inside if
2019-02-15 Eddie HungFixes needed for DFF circuits
2019-02-15 Eddie HungRefactor
2019-02-15 Eddie HungCope with width != 1 when re-mapping cells
2019-02-15 Jim LawsonRemoved unused variables, functions.
2019-02-15 Jim LawsonAppend (instead of over-writing) EXTRA_FLAGS
2019-02-15 Eddie Hungabc9 to stitch results with CI/CO properly
2019-02-15 Eddie Hungread_aiger with more asserts, and call clean
2019-02-15 Eddie Hungwrite_xaiger to cope with unknown cells by transforming...
2019-02-15 Jim LawsonUpdate cells supported for verilog to FIRRTL conversion.
2019-02-14 Eddie HungMore cleanup
2019-02-14 Eddie HungMore cleanup of write_xaiger
2019-02-14 Eddie HungGet rid of formal stuff from xaiger backend
2019-02-14 Eddie Hungsynth_ice40 to have new -abc9 arg
2019-02-14 Eddie HungLeave FIXME for clean
2019-02-14 Eddie HungUse module->addLut()
2019-02-14 Eddie HungFix stitching
2019-02-14 Eddie HungUse ConstEval to compute LUT masks
2019-02-13 Eddie HungMerge remote-tracking branch 'origin/read_aiger' into...
2019-02-13 Eddie HungMerge https://github.com/YosysHQ/yosys into xaig
2019-02-13 Eddie HungRip out some more stuff
2019-02-13 Clifford WolfFix sign handling of real constants
2019-02-13 Eddie HungRip out unused functions in abc9
2019-02-12 Eddie HungAdd support for read_aiger -wideports
2019-02-12 Eddie HungAdd support for read_aiger -map
2019-02-12 Eddie HungParse 'm' in xaiger
2019-02-12 Eddie HungWIP for ABC with aiger
next