yosys.git
2019-06-06 Eddie HungRun muxpack and muxcover in synth_xilinx
2019-06-06 Eddie HungRemove abc_flop attributes for now
2019-06-06 Eddie HungMerge remote-tracking branch 'origin/eddie/muxpack...
2019-06-06 Eddie HungFix and test for balanced case
2019-06-06 Eddie HungMerge remote-tracking branch 'origin/eddie/muxpack...
2019-06-06 Eddie HungFix warnings
2019-06-06 Eddie HungSupport cascading $pmux.A with $mux.A and $mux.B
2019-06-06 Eddie HungMore cleanup
2019-06-06 Eddie HungFix spacing
2019-06-06 Eddie HungNon chain user check using next_sig
2019-06-06 Eddie HungAdd non exclusive test
2019-06-06 Eddie HungMove muxpack from passes/techmap to passes/opt
2019-06-06 Eddie HungUpdate doc
2019-06-06 Eddie HungAdd to CHANGELOG
2019-06-06 Eddie HungOne more and tidy up
2019-06-06 Eddie HungAdd a few more special case tests
2019-06-06 Eddie HungAdd tests, fix for !=
2019-06-06 Eddie HungMissing file
2019-06-06 Eddie HungInitial adaptation of muxpack from shregmap
2019-06-06 Clifford WolfMerge pull request #1060 from antmicro/parsing_attr_on_...
2019-06-06 David ShahMerge pull request #1073 from whitequark/ecp5-diamond-iob
2019-06-06 whitequarkECP5: implement all Diamond I/O buffer primitives.
2019-06-06 Clifford WolfMerge pull request #1071 from YosysHQ/eddie/fix_1070
2019-06-06 Clifford WolfMerge pull request #1072 from YosysHQ/eddie/fix_1069
2019-06-05 Eddie HungMissing doc for -tech xilinx in shregmap
2019-06-05 Eddie HungError out if no top module given before 'sim'
2019-06-05 Eddie HungFix typo in opt_rmdff
2019-06-05 Eddie Hungshregmap -tech xilinx_static to handle INIT
2019-06-05 Eddie HungContinue support for ShregmapTechXilinx7Static
2019-06-05 Eddie HungUpdate abc attributes on FD*E_1
2019-06-05 Eddie HungCleanup
2019-06-05 Eddie HungCall shregmap -tech xilinx_static
2019-06-05 Eddie HungRevert "Move ff_map back after ABC for shregmap"
2019-06-05 Eddie HungAdd -tech xilinx_static
2019-06-05 Eddie HungRefactor to ShregmapTechXilinx7Static
2019-06-05 Eddie Hungshregmap -tech xilinx_dynamic to work -params and ...
2019-06-05 Eddie HungMerge pull request #1067 from YosysHQ/clifford/fix1065
2019-06-05 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-06-05 Eddie HungMerge remote-tracking branch 'origin/clifford/fix1065...
2019-06-05 Maciej KurcFixed memory leak.
2019-06-05 Clifford WolfMerge pull request #1066 from YosysHQ/clifford/fix1056
2019-06-05 Clifford WolfMajor rewrite of wire selection in setundef -init
2019-06-05 Clifford WolfIndent fix
2019-06-05 Clifford WolfMerge pull request #999 from jakobwenzel/setundefInitFix
2019-06-05 Clifford WolfFix typo in fmcombine log message, fixes #1063
2019-06-05 Clifford WolfSuppress driver-driver conflict warning for unknown...
2019-06-05 Clifford WolfRemove yosys_banner() from python wrapper init, fixes...
2019-06-04 Eddie HungRename shregmap -tech xilinx -> xilinx_dynamic
2019-06-04 Eddie HungAdd log_assert to ensure no loops
2019-06-04 Eddie HungOnly toposort builtin and abc types
2019-06-04 Eddie HungAdd space between -D and _ABC
2019-06-04 Eddie HungAdd (* abc_flop_q *) to brams_bb.v
2019-06-04 Eddie HungFix name clash
2019-06-04 Eddie HungAdd mux_map.v for wide mux
2019-06-04 Clifford WolfMerge pull request #1062 from tux3/patch-1
2019-06-04 Tux3README.md: Missing formatting for <tag>
2019-06-04 Maciej KurcMoved tests that fail with Icarus Verilog to /tests...
2019-06-04 Eddie HungMove ff_map back after ABC for shregmap
2019-06-04 Eddie HungRespect -nocarry
2019-06-04 Eddie HungFix pmux2shiftx logic
2019-06-04 Eddie HungMerge mistake
2019-06-04 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-06-04 Eddie HungMerge pull request #1061 from YosysHQ/eddie/techmap_and...
2019-06-04 Eddie HungTypo
2019-06-04 Eddie HungRemove extra newline
2019-06-04 Eddie HungIS_C_INVERTED
2019-06-04 Eddie HungExecute techmap and arith_map simultaneously
2019-06-03 Eddie HungFix `ifndef
2019-06-03 Eddie HungMake SB_LUT4 a whitebox, SB_DFF a blackbox (for now)
2019-06-03 Eddie HungAssert that box_unique_id is indeed unique
2019-06-03 Eddie HungRemove dupe
2019-06-03 Eddie HungSkip internal modules when generating box_unique_id
2019-06-03 Eddie HungWhen creating new holes cell, inherit parameters too
2019-06-03 Eddie HungOoopsie
2019-06-03 Eddie HungConsistent with xilinx
2019-06-03 Maciej KurcAdded tests for attributes
2019-06-02 Clifford WolfOnly support Symbiotic EDA flavored Verific
2019-06-01 Eddie HungAdd flops as blackboxes
2019-06-01 Eddie HungAdd FD*E_1 -> FD*E techmap rules
2019-06-01 Eddie HungTechmap flops before ABC again
2019-06-01 Eddie Hungparse_xaiger to cope with flops
2019-05-31 Eddie HungABC9 to understand flops
2019-05-31 Eddie HungMerge branch 'xaig' into xc7mux
2019-05-31 Eddie HungThrow out unused code inherited from abc
2019-05-31 Maciej KurcAdded support for parsing attributes on port connections.
2019-05-31 Clifford WolfFix "tee" handling of log_streams
2019-05-30 Eddie HungFix issue where keep signal became PI, but also box...
2019-05-30 Eddie Hungread_xaiger() to name box signals
2019-05-30 Eddie HungFix spelling
2019-05-30 Eddie HungRemove whitebox attribute from DRAMs for now
2019-05-30 Eddie HungDo not re-sort box_module ports
2019-05-30 Eddie HungRemove whitespace
2019-05-30 Eddie HungRevert "Re-enable &dc2"
2019-05-30 Eddie HungDo not double count LUT1s
2019-05-30 Eddie HungCarry in/out to be the last input/output for chains...
2019-05-30 Clifford WolfEnable Verific flag veri_elaborate_top_level_modules_ha...
2019-05-30 Clifford WolfMerge pull request #1057 from mmicko/fix_478
2019-05-30 Eddie HungRe-enable &dc2
2019-05-30 Eddie HungReduce -W to 160
2019-05-30 Eddie HungSome more realistic delays...
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