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microwatt.git
2019-09-24
Anton Blanchard
Merge pull request #71 from antonblanchard/dependencies
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2019-09-24
Anton Blanchard
Update Makefile dependencies
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2019-09-24
Anton Blanchard
Merge branch 'divider' of https://github.com/paulusmack...
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2019-09-24
Anton Blanchard
Merge pull request #70 from antonblanchard/badly-named...
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2019-09-24
Anton Blanchard
Rename OP_SUBFC -> OP_SUBFE, OP_ADDC -> OP_ADDE
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2019-09-24
Anton Blanchard
Merge pull request #69 from antonblanchard/debug-module
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2019-09-23
Anton Blanchard
Terminate test on illegal instruction
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2019-09-23
Anton Blanchard
Fix ghdl error
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2019-09-23
Anton Blanchard
Add core_debug.vhdl to fusesoc configs
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2019-09-23
Paul Mackerras
Speed up the divider a little
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2019-09-23
Paul Mackerras
Add a divider unit and a testbench for it
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2019-09-20
Benjamin Herrenschmidt
Add distclean to Makefile
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2019-09-20
Benjamin Herrenschmidt
New C based JTAG debug tool
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2019-09-20
Benjamin Herrenschmidt
Add core debug module
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2019-09-20
Benjamin Herrenschmidt
Add jtag support in simulation via a socket
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2019-09-20
Benjamin Herrenschmidt
Add DMI address decoder
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2019-09-20
Benjamin Herrenschmidt
Wishbone debug module
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2019-09-20
Benjamin Herrenschmidt
Add a debug (DMI) bus and a JTAG interface to it on...
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2019-09-20
Benjamin Herrenschmidt
Use a 3 way WB arbiter and cleanup fpga toplevel
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2019-09-19
Anton Blanchard
Merge pull request #66 from antonblanchard/reformat-4
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2019-09-19
Anton Blanchard
Reformat crhelpers, and remove some stale code
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2019-09-19
Anton Blanchard
Reformat helpers
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2019-09-19
Anton Blanchard
Reformat insn_helpers
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2019-09-19
Anton Blanchard
Merge pull request #65 from antonblanchard/loadstore-opt
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2019-09-19
Anton Blanchard
Reformat loadstore1
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2019-09-19
Anton Blanchard
Reformat loadstore2
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2019-09-19
Anton Blanchard
loads don't do both byte reversal and sign extension
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2019-09-19
Anton Blanchard
Merge pull request #64 from antonblanchard/reformat-3
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2019-09-19
Anton Blanchard
Merge pull request #63 from antonblanchard/multiply...
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2019-09-19
Anton Blanchard
Reformat wishbone code
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2019-09-19
Anton Blanchard
Reformat glibc_random
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2019-09-19
Anton Blanchard
Reformat simple_ram_behavioural
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2019-09-19
Anton Blanchard
Reformat sim_console
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2019-09-19
Anton Blanchard
Reformat multiply_tb
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2019-09-19
Anton Blanchard
Reformat execute2
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2019-09-19
Anton Blanchard
Reformat CR file
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2019-09-19
Anton Blanchard
Reformat register file
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2019-09-19
Anton Blanchard
Reformat multiply code
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2019-09-19
Anton Blanchard
Don't use VHDL 2008 condition operator in multiply
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2019-09-16
Anton Blanchard
Merge pull request #62 from antonblanchard/byte-reverse...
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2019-09-16
Anton Blanchard
Merge pull request #61 from antonblanchard/execute...
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2019-09-16
Anton Blanchard
Move byte reversal of stores to first cycle
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2019-09-16
Anton Blanchard
execute1 no longer needs sim_console
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2019-09-15
Anton Blanchard
Merge pull request #60 from antonblanchard/testbenches
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2019-09-15
Anton Blanchard
Fix multiply_tb
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2019-09-15
Anton Blanchard
Add an icache testbench
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2019-09-15
Anton Blanchard
Merge pull request #56 from antonblanchard/writeback...
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2019-09-15
Anton Blanchard
Remove cycle in writeback
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2019-09-15
Anton Blanchard
Merge pull request #59 from antonblanchard/trap-decode
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2019-09-15
Anton Blanchard
Merge pull request #58 from antonblanchard/decode2...
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2019-09-15
Anton Blanchard
Fix make check
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2019-09-15
Anton Blanchard
Fix spurious outstanding assert
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2019-09-15
Anton Blanchard
Merge pull request #57 from antonblanchard/add-nop
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2019-09-15
Anton Blanchard
Add a decode for the nop instruction
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2019-09-15
Anton Blanchard
Merge pull request #55 from antonblanchard/fetch-fix
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2019-09-15
Anton Blanchard
Add a default value for RESET_ADDRESS
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2019-09-14
Anton Blanchard
Merge pull request #51 from antonblanchard/writeback-fix
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2019-09-14
Anton Blanchard
Reformat writeback.vhdl
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2019-09-14
Anton Blanchard
Exit if we try to write more than one GPR or CR in...
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2019-09-12
Anton Blanchard
Merge pull request #50 from antonblanchard/decode1-opt
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2019-09-12
Anton Blanchard
No need to gate nia or insn in decode1
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2019-09-12
Anton Blanchard
Merge pull request #49 from antonblanchard/icache-2
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2019-09-12
Anton Blanchard
Add a simple direct mapped icache
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2019-09-12
Anton Blanchard
SOC memory wishbone should clear ACK regardless of STB
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2019-09-12
Anton Blanchard
Merge pull request #48 from antonblanchard/clk_gen_bypass
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2019-09-12
Anton Blanchard
Fix clk_gen_bypass
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2019-09-11
Anton Blanchard
Merge pull request #47 from antonblanchard/if-fix
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2019-09-11
Anton Blanchard
Merge pull request #46 from antonblanchard/record-fix
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2019-09-11
Anton Blanchard
Explicitly check against '1' in if statements
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2019-09-11
Anton Blanchard
Remove names from end record statements
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2019-09-11
Anton Blanchard
Merge pull request #45 from antonblanchard/fixes
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2019-09-11
Anton Blanchard
Fix issue in loadstore1
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2019-09-11
Anton Blanchard
Fix issue in execute2
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2019-09-11
Anton Blanchard
Merge pull request #44 from antonblanchard/nia-remove
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2019-09-11
Anton Blanchard
Remove nia from loadstore and multiply
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2019-09-11
Anton Blanchard
Merge pull request #43 from mikey/trivial
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2019-09-11
Michael Neuling
Remove FIXME comment
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2019-09-11
Anton Blanchard
Merge pull request #41 from mikey/travis
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2019-09-11
Anton Blanchard
Merge pull request #42 from antonblanchard/fetch-rework-v2
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2019-09-11
Anton Blanchard
Reformat core.vhdl
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2019-09-11
Anton Blanchard
Remove sim console
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2019-09-11
Anton Blanchard
Reduce multiply to 2 cycles
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2019-09-11
Anton Blanchard
Register outputs on writeback
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2019-09-11
Anton Blanchard
Register outputs on execute2
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2019-09-11
Anton Blanchard
Register outputs on loadstore1
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2019-09-11
Anton Blanchard
Move debug execute output into decode2
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2019-09-11
Anton Blanchard
Rework pipeline, add stall and flush signals
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2019-09-11
Michael Neuling
Allow a full make check on Travis
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2019-09-10
Anton Blanchard
Merge pull request #40 from antonblanchard/makefile...
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2019-09-10
Anton Blanchard
Update Makefile dependencies
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2019-09-10
Benjamin Herrenschmidt
Switch soc to use std_ulogic
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2019-09-10
Benjamin Herrenschmidt
Share soc.vhdl between FPGA and sim
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2019-09-10
Benjamin Herrenschmidt
Pass wishbone record to bram memory module
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2019-09-10
Benjamin Herrenschmidt
Rework wishbone slave address decoding
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2019-09-10
Benjamin Herrenschmidt
Move wishbone arbiter out of the core
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2019-09-10
Benjamin Herrenschmidt
Re-indent and reformat soc.vhdl
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2019-09-10
Benjamin Herrenschmidt
Split FPGA toplevel from soc
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2019-09-10
Anton Blanchard
Merge pull request #39 from antonblanchard/no-x-state
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2019-09-10
Anton Blanchard
Don't send out X state from the memory behavioural
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2019-09-10
Anton Blanchard
Merge pull request #36 from mikey/gitignore
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