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yosys.git
2014-02-05
Clifford Wolf
Removed old unused files from tests/
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2014-02-04
Clifford Wolf
Added support for dump -append
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2014-02-04
Clifford Wolf
Throw errors if non-existing selection variables are...
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2014-02-04
Clifford Wolf
Added select -none
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2014-02-04
Clifford Wolf
presentation progress
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2014-02-04
Clifford Wolf
Fixed detection of init attribute in opt_rmdff
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2014-02-04
Clifford Wolf
Added support for inline commands to abc -script
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2014-02-04
Clifford Wolf
presentation progress
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2014-02-04
Clifford Wolf
Added hierarchy -purge_lib option
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2014-02-04
Clifford Wolf
Added test cases for sat command
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2014-02-04
Clifford Wolf
added sat -falsify
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2014-02-04
Clifford Wolf
Fixed bug in sequential sat proofs and improved handlin...
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2014-02-04
Clifford Wolf
Improved handling of reg init in opt_share and opt_rmdff
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2014-02-03
Clifford Wolf
presentation progress
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2014-02-03
Clifford Wolf
presentation progress
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2014-02-03
Clifford Wolf
Addred sat option -ignore_unknown_cells
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2014-02-03
Clifford Wolf
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
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2014-02-03
Clifford Wolf
Replaced isim with xsim in tests/tools/autotest.sh...
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2014-02-02
Clifford Wolf
More opt_const -mux_bool features
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2014-02-02
Clifford Wolf
presentation progress
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2014-02-02
Clifford Wolf
Added opt_const -mux_bool
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2014-02-02
Clifford Wolf
Added support for inverter chains to opt_const
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2014-02-02
Clifford Wolf
Added RTLIL::SigSpec::to_single_sigbit()
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2014-02-02
Clifford Wolf
Only generate write-enable $and if WE is not constant...
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2014-02-02
Clifford Wolf
Added constant-clock case to opt_rmdff
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2014-02-02
Clifford Wolf
presentation progress
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2014-02-02
Clifford Wolf
Added show -notitle option
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2014-02-02
Clifford Wolf
Added delete command
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2014-02-02
Clifford Wolf
Added suuport for module attribute matching with A...
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2014-02-02
Clifford Wolf
presentation progress
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2014-02-02
Clifford Wolf
presentation progress
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2014-02-02
Clifford Wolf
Added support for blanks after -I and -D in read_verilog
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2014-02-01
Clifford Wolf
Fixed a bug in miter command
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2014-02-01
Clifford Wolf
Added sat -show-inputs and -show-outputs
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2014-02-01
Clifford Wolf
Added show -color support for cells and finished show...
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2014-02-01
Clifford Wolf
Fixed comment/eol parsing in ilang frontend
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2014-02-01
Clifford Wolf
Added constant size expression support of sized constants
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2014-02-01
Clifford Wolf
Added note about SystemVerilog assert statement to...
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2014-02-01
Clifford Wolf
Added miter command
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2014-01-31
Clifford Wolf
Progress on presentation
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2014-01-31
Clifford Wolf
More changes to techlibs/common/simlib.v for LEC
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2014-01-30
Clifford Wolf
presentation progress
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2014-01-30
Clifford Wolf
Bugfix in name resolution with generate blocks
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2014-01-30
Clifford Wolf
Added yosys -H for command list
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2014-01-29
Clifford Wolf
presentation progress
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2014-01-29
Clifford Wolf
presentation progress
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2014-01-29
Clifford Wolf
Tiny change in example script in README
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2014-01-29
Clifford Wolf
Added -h command line option
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2014-01-29
Clifford Wolf
Added test comments to techlibs/cmos/cmos_cells.lib
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2014-01-29
Clifford Wolf
Updated ABC to hg rev e6b09e1
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2014-01-28
Clifford Wolf
Added read_verilog -icells option
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2014-01-28
Clifford Wolf
Major rewrite of techlibs/common/simlib.v for LEC ...
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2014-01-28
Clifford Wolf
presentation progress
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2014-01-28
Clifford Wolf
Renamed manual/FILES_* directories
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2014-01-28
Clifford Wolf
Progress on presentation
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2014-01-27
Clifford Wolf
Progress on presentation
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2014-01-27
Clifford Wolf
Added first presentation slides
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2014-01-26
Clifford Wolf
Merge branch 'btor' of https://github.com/ahmedirfan198...
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2014-01-26
Clifford Wolf
Merge pull request #21 from hansiglaser/master
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2014-01-25
Johann Glaser
enabled multiple "-map" for the extract pass
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2014-01-25
Johann Glaser
beautified write_intersynth
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2014-01-25
Ahmed Irfan
root bug corrected
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2014-01-25
Clifford Wolf
Added support for // comments in liberty parser
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2014-01-24
Clifford Wolf
Merge branch 'btor'
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2014-01-24
Ahmed Irfan
removed regex include
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2014-01-24
Ahmed Irfan
merged clifford changes + removed regex
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2014-01-24
Clifford Wolf
Use techmap -share_map in btor scripts
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2014-01-24
Clifford Wolf
Moved btor scripts to backends/btor/
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2014-01-24
Clifford Wolf
Restored Makefile
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2014-01-24
Clifford Wolf
Restored IdString::check()
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2014-01-24
Clifford Wolf
Merge branch 'btor' of https://github.com/ahmedirfan198...
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2014-01-24
Clifford Wolf
Fixed handling of unsized constants in verilog frontend
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2014-01-24
Ahmed Irfan
minor change in script
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2014-01-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-01-20
Clifford Wolf
Fixed algorithmic complexity of AST simplification...
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2014-01-20
Ahmed Irfan
slice bug corrected
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2014-01-20
Ahmed Irfan
assert feature
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2014-01-20
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-01-19
Clifford Wolf
Added hilomap command
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2014-01-19
Clifford Wolf
Added sat -tempinduc and sat -prove-asserts
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2014-01-19
Clifford Wolf
Added $assert support to satgen
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2014-01-19
Clifford Wolf
Added $assert cell
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2014-01-19
Clifford Wolf
Added Verilog parser support for asserts
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2014-01-18
Ahmed Irfan
script added
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2014-01-18
Ahmed Irfan
Merge branch 'master' of https://github.com/ahmedirfan1...
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2014-01-18
Clifford Wolf
Fixed $lut simlib model for a wider range of tools
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2014-01-18
Clifford Wolf
Fixed parsing of verilog macros at end of line
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2014-01-18
Clifford Wolf
More changes to simlib to make it friendlier to a wider...
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2014-01-18
Clifford Wolf
Fixed a type in $mem model in simlib.v
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2014-01-18
Ahmed Irfan
Merge branch 'master' of https://github.com/ahmedirfan1...
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2014-01-18
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-01-18
Ahmed Irfan
pmux2mux
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2014-01-18
Clifford Wolf
Removed cases of trailing comma in stdcells.v
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2014-01-18
Clifford Wolf
Added $bu0 cell to simlib.v
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2014-01-18
Clifford Wolf
Improved setundef random number generator
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2014-01-17
Clifford Wolf
Added setundef command
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2014-01-17
Clifford Wolf
Some improvements in log_dump_val_worker() templates
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2014-01-17
Clifford Wolf
Added techlibs/common/pmux2mux.v
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2014-01-17
Ahmed Irfan
verilog default options pull
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2014-01-17
Ahmed Irfan
Merge branch 'master' of https://github.com/ahmedirfan1...
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