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libreriscv.git
2020-11-13
lkcl
(no commit message)
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2020-11-13
Cesar_Strauss
Add Tomasulo model example
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2020-11-13
lkcl
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2020-11-13
lkcl
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2020-11-13
lkcl
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2020-11-13
lkcl
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2020-11-11
lkcl
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2020-11-11
lkcl
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2020-11-11
lkcl
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2020-11-11
Tobias Platen
add dcbz and tlbio instruction needed by mmu
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2020-11-10
Luke Kenneth...
add minerva nmigen-soc example
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2020-11-09
lkcl
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2020-11-09
lkcl
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2020-11-09
lkcl
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2020-11-05
Luke Kenneth...
add EOMA68+LibreSOC gadie section
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2020-11-05
Luke Kenneth...
add EOMA68+LibreSOC gadie section
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2020-11-05
Luke Kenneth...
extend gaddie pitch
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2020-11-05
Luke Kenneth...
extend gaddie pitch
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2020-11-05
Luke Kenneth...
extend gaddie pitch
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2020-11-05
Luke Kenneth...
add gaddie pitch section for LibreSOC
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2020-11-05
Luke Kenneth...
update nlnet FAQ
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2020-11-05
Luke Kenneth...
update FAQ
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2020-11-05
Luke Kenneth...
add name tag to FAQ
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2020-11-05
Luke Kenneth...
add name tag to FAQ
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2020-11-05
Luke Kenneth...
add name tag to FAQ
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2020-11-04
Luke Kenneth...
add to nlnet FAQ
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2020-11-04
colepoirier...
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2020-11-04
Luke Kenneth...
add to NLnet FAQ
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2020-11-04
Luke Kenneth...
add to NLnet FAQ
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2020-11-04
Luke Kenneth...
show tab on imag
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2020-11-04
Luke Kenneth...
update FPGA connector images
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2020-11-04
Luke Kenneth...
add circuit refs
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2020-11-04
Luke Kenneth...
change to use 3.3v on VERSA X3
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2020-11-04
Luke Kenneth...
add NLnet FAQ
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2020-11-04
colepoirier...
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2020-11-04
Cole Poirier
HDL_wokflow update ulx3s jtag jumper wire connection...
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2020-11-04
Cole Poirier
HDL_workflow/ECP5_FPGA provide two images showing diffe...
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2020-11-04
colepoirier...
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2020-11-04
colepoirier...
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2020-11-04
Cole Poirier
update photo for stlinkv2 JTAG wires in HDL_Workflow...
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2020-11-04
colepoirier...
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2020-11-04
colepoirier...
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2020-11-03
Luke Kenneth...
colour-mark X3 VERSA ECP5 JTAG pins
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2020-11-03
Luke Kenneth...
update jtag table, add colour to images
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2020-11-03
Luke Kenneth...
add stlinkv2 photos
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2020-11-03
Luke Kenneth...
add stlinkv2 connector images
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2020-11-03
Luke Kenneth...
swap wires around to match ulx3s
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2020-11-03
Luke Kenneth...
format table
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2020-11-03
Luke Kenneth...
add ECP5 JTAG connections
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2020-11-03
Luke Kenneth...
add image links to ECP5 page
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2020-11-03
Luke Kenneth...
add versa ecp5 x3 photo
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2020-11-03
Luke Kenneth...
add VERSA-ECP5 images, rename FPGA page
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2020-11-01
colepoirier...
(no commit message)
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2020-11-01
colepoirier...
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2020-11-01
Cole Poirier
add images to wiki for ulx3s jtag stlinkv2 wires
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2020-11-01
colepoirier...
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2020-11-01
colepoirier...
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2020-11-01
colepoirier...
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2020-11-01
colepoirier...
add page use ulx3s fpga gpio pins for Libre-SOC JTAG...
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2020-10-31
Luke Kenneth...
add cross-ref links
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2020-10-31
Luke Kenneth...
adjust image size
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2020-10-31
Luke Kenneth...
add description of table
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2020-10-31
Luke Kenneth...
change image size
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2020-10-31
Luke Kenneth...
add image size
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2020-10-31
Luke Kenneth...
add start of isa-to-virtual regs
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2020-10-31
Luke Kenneth...
add isa to virtual regs lookup
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2020-10-30
Luke Kenneth...
add clock switch resource
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2020-10-30
Luke Kenneth...
spelling
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2020-10-30
Luke Kenneth...
add 180nm tapeout to progress
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2020-10-29
colepoirier...
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2020-10-29
colepoirier...
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2020-10-29
Luke Kenneth...
whitespace
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2020-10-29
lkcl
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2020-10-29
lkcl
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2020-10-27
Luke Kenneth...
further investigation note
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2020-10-27
Luke Kenneth...
further investigation note
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2020-10-27
Luke Kenneth...
further investigation note
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2020-10-27
Jacob Lifshay
add header
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2020-10-27
Jacob Lifshay
finish compared_to_register_renaming.mdwn
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2020-10-27
Luke Kenneth...
add link to tomasulo_transformation for notes on "namel...
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2020-10-27
Jacob Lifshay
working on compared_to_register_renaming.mdwn
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2020-10-27
colepoirier...
(no commit message)
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2020-10-27
lkcl
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2020-10-27
lkcl
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2020-10-26
lkcl
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2020-10-26
lkcl
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2020-10-26
lkcl
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2020-10-26
lkcl
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2020-10-26
lkcl
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2020-10-26
lkcl
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2020-10-26
lkcl
(no commit message)
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2020-10-26
lkcl
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2020-10-26
lkcl
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2020-10-26
lkcl
(no commit message)
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2020-10-26
lkcl
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2020-10-26
lkcl
(no commit message)
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2020-10-26
lkcl
(no commit message)
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2020-10-26
lkcl
(no commit message)
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2020-10-26
lkcl
(no commit message)
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2020-10-26
lkcl
(no commit message)
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