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yosys.git
2014-02-12
Clifford Wolf
Updated ABC to rev e97a6e1d59b9
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2014-02-11
Clifford Wolf
renamed ilang "scope error" to "ilang error"
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2014-02-11
Clifford Wolf
More Makefile cleanups
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2014-02-11
Clifford Wolf
Improved "make manual" and "make clean"
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2014-02-09
Clifford Wolf
Improved ilang parser error messages
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2014-02-09
Clifford Wolf
fixed a bug in subcircuit library with cells that have...
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2014-02-09
Clifford Wolf
Various improvements in expose command (added -sep...
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2014-02-09
Clifford Wolf
Added delete {-input|-output|-port}
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2014-02-09
Clifford Wolf
Bugfix in delete command
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2014-02-08
Clifford Wolf
Added test cases for expose -evert-dff
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2014-02-08
Clifford Wolf
Fixed handling of async reset in expose -evert-dff
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2014-02-08
Clifford Wolf
Build fixes for log cmd
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2014-02-08
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-08
Clifford Wolf
Implemented expose -evert-dff
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2014-02-08
Clifford Wolf
Merge pull request #24 from hansiglaser/master
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2014-02-08
Johann Glaser
added "log" command
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2014-02-08
Clifford Wolf
Improved checking of internal cell conventions
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2014-02-08
Clifford Wolf
Fixed bug in collecting of RD_TRANSPARENT parameter...
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2014-02-08
Clifford Wolf
Added various new options to splice command
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2014-02-08
Clifford Wolf
Added %a select operator
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2014-02-08
Clifford Wolf
Moved some passes to other source directories
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2014-02-08
Clifford Wolf
Added support for "keep" attribute to abc pass
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2014-02-08
Clifford Wolf
Added opt -purge (frontend to opt_clean -purge)
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2014-02-08
Clifford Wolf
Only count non-trivial attributes when findinf master...
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2014-02-08
Clifford Wolf
Added checking for ABC modifications to Makefile and...
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2014-02-07
Clifford Wolf
Now also move net labes to the right position in splice cmd
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2014-02-07
Clifford Wolf
Improved detection of primary wire for a signal in...
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2014-02-07
Clifford Wolf
Added splice command
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2014-02-07
Clifford Wolf
Added log_header() to splitnets
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2014-02-07
Clifford Wolf
Added $slice and $concat to CellTypes list
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2014-02-07
Clifford Wolf
Added $slice and $concat cell types
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2014-02-07
Clifford Wolf
Stronger checking of internal cells
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2014-02-07
Clifford Wolf
Re-enabled abc "retime" after sorting yout the yosys...
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2014-02-07
Clifford Wolf
Added echo command
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2014-02-07
Clifford Wolf
Fixed use of "cmd_error" in passes/cmds/design.cc
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2014-02-06
Clifford Wolf
Fixed gcc compiler warnings with release build
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2014-02-06
Clifford Wolf
Disabled ABC retime for now (elliptic_curve_group testc...
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2014-02-06
Clifford Wolf
Updated ABC to rev 10cc13a2a0f1
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2014-02-06
Clifford Wolf
Added "retime" to standard ABC recipes
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2014-02-06
Clifford Wolf
Added copy command
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2014-02-06
Clifford Wolf
Added design -stash/-copy-from/-copy-to
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2014-02-06
Clifford Wolf
Added support for s: select expressions (wire width)
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2014-02-06
Clifford Wolf
Added i:, o:, and x: selection pattern
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2014-02-06
Clifford Wolf
Added support for %m selection op
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2014-02-06
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-06
Clifford Wolf
Added generic RTLIL::SigSpec::parse_sel() with support...
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2014-02-06
Clifford Wolf
Merge pull request #23 from hansiglaser/master
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2014-02-06
Johann Glaser
new %s: add sub-modules to selection
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2014-02-06
Clifford Wolf
Added support for sat -show @<sel_name>
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2014-02-06
Clifford Wolf
Added sat -set-init-def and sat -tempinduct-def
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2014-02-06
Clifford Wolf
Added opt_const -undriven
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2014-02-06
Clifford Wolf
Added expose -dff
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2014-02-06
Clifford Wolf
Added support for #-comments in same line as command
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2014-02-06
Clifford Wolf
presentation progress
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2014-02-06
Clifford Wolf
Changed techmap description from "simple" to "generic"
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2014-02-06
Clifford Wolf
Added miter -make_outcmp
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2014-02-06
Clifford Wolf
Added sat -set-init-zero support
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2014-02-06
Clifford Wolf
Added support for backslash continuation in script...
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2014-02-06
Clifford Wolf
Added counters sat test case
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2014-02-05
Clifford Wolf
Added sat -verify and -falsify support for non-prove...
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2014-02-05
Clifford Wolf
Added expose command
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2014-02-05
Clifford Wolf
presentation progress
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2014-02-05
Clifford Wolf
Simplified select "Assertation failed" message generation
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2014-02-05
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-05
Clifford Wolf
Merge pull request #22 from hansiglaser/master
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2014-02-05
Clifford Wolf
Added BTOR backend README file
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2014-02-05
Clifford Wolf
Added selection support for r: and selection with relat...
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2014-02-05
Johann Glaser
be more verbose for select -assert-any and -assert...
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2014-02-05
Johann Glaser
improved help for "select"
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2014-02-05
Clifford Wolf
presentation progress
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2014-02-05
Clifford Wolf
presentation progress
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2014-02-05
Clifford Wolf
Added read_verilog -setattr
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2014-02-05
Clifford Wolf
Added setattr and setparam commands
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2014-02-05
Clifford Wolf
Updated todo items in README file
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2014-02-05
Clifford Wolf
Removed old unused files from tests/
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2014-02-04
Clifford Wolf
Added support for dump -append
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2014-02-04
Clifford Wolf
Throw errors if non-existing selection variables are...
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2014-02-04
Clifford Wolf
Added select -none
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2014-02-04
Clifford Wolf
presentation progress
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2014-02-04
Clifford Wolf
Fixed detection of init attribute in opt_rmdff
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2014-02-04
Clifford Wolf
Added support for inline commands to abc -script
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2014-02-04
Clifford Wolf
presentation progress
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2014-02-04
Clifford Wolf
Added hierarchy -purge_lib option
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2014-02-04
Clifford Wolf
Added test cases for sat command
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2014-02-04
Clifford Wolf
added sat -falsify
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2014-02-04
Clifford Wolf
Fixed bug in sequential sat proofs and improved handlin...
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2014-02-04
Clifford Wolf
Improved handling of reg init in opt_share and opt_rmdff
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2014-02-03
Clifford Wolf
presentation progress
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2014-02-03
Clifford Wolf
presentation progress
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2014-02-03
Clifford Wolf
Addred sat option -ignore_unknown_cells
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2014-02-03
Clifford Wolf
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
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2014-02-03
Clifford Wolf
Replaced isim with xsim in tests/tools/autotest.sh...
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2014-02-02
Clifford Wolf
More opt_const -mux_bool features
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2014-02-02
Clifford Wolf
presentation progress
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2014-02-02
Clifford Wolf
Added opt_const -mux_bool
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2014-02-02
Clifford Wolf
Added support for inverter chains to opt_const
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2014-02-02
Clifford Wolf
Added RTLIL::SigSpec::to_single_sigbit()
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2014-02-02
Clifford Wolf
Only generate write-enable $and if WE is not constant...
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2014-02-02
Clifford Wolf
Added constant-clock case to opt_rmdff
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2014-02-02
Clifford Wolf
presentation progress
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