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yosys.git
2019-08-03
Miodrag Milanovic
Initial EFINIX support
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2019-08-02
Clifford Wolf
Merge pull request #1238 from mmicko/vsbuild_fix
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2019-08-02
Clifford Wolf
Merge pull request #1239 from mmicko/mingw_fix
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2019-08-01
Eddie Hung
Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map
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2019-08-01
Miodrag Milanovic
Fix linking issue for new mxe and pthread
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2019-08-01
Miodrag Milanovic
Fix yosys linking for mxe
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2019-08-01
Miodrag Milanovic
New mxe hacks needed to support 2ca237e
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2019-08-01
Miodrag Milanovic
Fix formatting for msys2 mingw build using GetSize
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2019-07-31
Clifford Wolf
Merge pull request #1233 from YosysHQ/clifford/defer
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2019-07-31
Miodrag Milanovic
Visual Studio build fix
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2019-07-29
Eddie Hung
RST -> RSTBRST for RAMB8BWER
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2019-07-29
Eddie Hung
Merge pull request #1228 from YosysHQ/dave/yy_buf_size
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2019-07-29
David Shah
Merge pull request #1234 from mmicko/fix_gzip_no_exist
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2019-07-29
Miodrag Milanovic
Fix case when file does not exist
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2019-07-29
Clifford Wolf
Update README to use "read" instead of "read_verilog"
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2019-07-29
Clifford Wolf
Call "read_verilog" with -defer from "read"
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2019-07-27
David Shah
Merge pull request #1226 from YosysHQ/dave/gzip
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2019-07-26
David Shah
Update CHANGELOG
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2019-07-26
David Shah
verilog_lexer: Increase YY_BUF_SIZE to 65536
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2019-07-26
David Shah
Fix frontend auto-detection for gzipped input
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2019-07-26
David Shah
Add support for reading gzip'd input files
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2019-07-25
Eddie Hung
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-07-25
Eddie Hung
Bump abc to fix &mfs bug
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2019-07-25
Clifford Wolf
Merge branch 'ZirconiumX-synth_intel_m9k'
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2019-07-25
Clifford Wolf
Merge pull request #1218 from ZirconiumX/synth_intel_iopads
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2019-07-25
Clifford Wolf
Merge pull request #1219 from jakobwenzel/objIterator
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2019-07-25
Eddie Hung
Merge pull request #1224 from YosysHQ/xilinx_fix_ff
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2019-07-25
Jakob Wenzel
replaced std::iterator with using statements
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2019-07-25
David Shah
xilinx: Fix missing cell name underscore in cells_map.v
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2019-07-24
Eddie Hung
Merge pull request #1222 from koriakin/s6-example
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2019-07-24
Marcin KoĆcielnicki
Add a simple example for Spartan 6
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2019-07-24
Jakob Wenzel
made ObjectIterator extend std::iterator
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2019-07-24
Dan Ravensloft
intel: Make -noiopads the default
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2019-07-23
Dan Ravensloft
intel: Map M9K BRAM only on families that have it
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2019-07-23
Eddie Hung
Merge pull request #1212 from YosysHQ/eddie/signed_ice4...
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2019-07-22
Eddie Hung
Merge pull request #1214 from jakobwenzel/astmod_clone
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2019-07-22
Jakob Wenzel
initialize noblackbox and nowb in AstModule::clone
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2019-07-20
Clifford Wolf
Add "stat -tech cmos"
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2019-07-19
David Shah
ice40: Fix test_dsp_model.sh
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2019-07-19
David Shah
ice40/cells_sim.v: Fix sign of J and K partial products
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2019-07-19
David Shah
ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
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2019-07-19
Eddie Hung
Add tests for all combinations of A and B signedness...
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2019-07-19
Eddie Hung
Don't copy ref if exists already
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2019-07-18
David Shah
Merge pull request #1208 from ZirconiumX/intel_cleanups
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2019-07-18
Dan Ravensloft
synth_intel: Use stringf
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2019-07-18
David Shah
Merge pull request #1207 from ZirconiumX/intel_new_pass...
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2019-07-18
Dan Ravensloft
synth_intel: s/not family/no family/
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2019-07-18
Dan Ravensloft
synth_intel: revert change to run_max10
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2019-07-18
Ben Widawsky
intel_synth: Fix help message
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2019-07-18
Ben Widawsky
intel_synth: Small code cleanup to remove if ladder
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2019-07-18
Ben Widawsky
intel_synth: Make family explicit and match
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2019-07-18
Ben Widawsky
intel_synth: Minor code cleanups
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2019-07-18
Dan Ravensloft
synth_intel: rename for consistency with #1184
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2019-07-18
Clifford Wolf
Merge pull request #1184 from whitequark/synth-better...
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2019-07-18
Clifford Wolf
Merge pull request #1203 from whitequark/write_verilog...
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2019-07-17
Clifford Wolf
Remove old $pmux_safe code from write_verilog
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2019-07-17
David Shah
Merge pull request #1204 from smunaut/fix_1187
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2019-07-16
Sylvain Munaut
ice40: Adapt the relut process passes to the new $lut...
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2019-07-16
whitequark
write_verilog: dump zero width constants correctly.
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2019-07-16
Eddie Hung
Merge pull request #1202 from YosysHQ/cmp2lut_lut6
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2019-07-16
whitequark
synth_ecp5: rename dram to lutram everywhere.
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2019-07-16
whitequark
synth_{ice40,ecp5}: more sensible pass label naming.
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2019-07-16
Eddie Hung
gen_lut to return correctly sized LUT mask
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2019-07-16
Eddie Hung
Forgot to commit
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2019-07-16
Eddie Hung
Add tests for cmp2lut on LUT6
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2019-07-16
Eddie Hung
Merge pull request #1188 from YosysHQ/eddie/abc9_push_i...
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2019-07-16
Eddie Hung
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
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2019-07-16
Clifford Wolf
Merge pull request #1200 from mmicko/fix_typo_liberty_cc
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2019-07-16
Clifford Wolf
Merge pull request #1199 from mmicko/extract_fa_fix
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2019-07-16
Miodrag Milanovic
Fix typo, double "of"
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2019-07-16
Miodrag Milanovic
Fix check logic in extract_fa
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2019-07-15
Eddie Hung
Merge pull request #1196 from YosysHQ/eddie/fix1178
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2019-07-15
Eddie Hung
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per ...
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2019-07-15
Clifford Wolf
Merge pull request #1189 from YosysHQ/eddie/fix1151
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2019-07-15
Clifford Wolf
Merge pull request #1190 from YosysHQ/eddie/fix_1099
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2019-07-15
Clifford Wolf
Merge pull request #1191 from whitequark/opt_lut-log_debug
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2019-07-15
Clifford Wolf
Merge pull request #1195 from Roman-Parise/master
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2019-07-15
Clifford Wolf
Merge pull request #1197 from nakengelhardt/handle...
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2019-07-15
Eddie Hung
Revert "Add log_checkpoint function and use it in opt_m...
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2019-07-15
N. Engelhardt
smt: handle failure of setrlimit syscall
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2019-07-15
Eddie Hung
Revert "Fix first divergence in #1178"
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2019-07-15
Eddie Hung
Merge branch 'master' into eddie/fix1178
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2019-07-15
Clifford Wolf
Redesign log_id_cache so that it doesn't keep IdString...
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2019-07-15
Clifford Wolf
Add log_checkpoint function and use it in opt_muxtree
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2019-07-14
Eddie Hung
Merge pull request #1194 from cr1901/miss-semi
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2019-07-14
William D....
Fix missing semicolon in Windows-specific code in aiger...
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2019-07-14
Roman-Parise
Updated FreeBSD dependencies in README.md
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2019-07-13
whitequark
opt_lut: make less chatty.
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2019-07-13
Eddie Hung
If ConstEval fails do not log_abort() but return gracefully
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2019-07-13
Eddie Hung
Error out if enable > dbits
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2019-07-13
Eddie Hung
ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT
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2019-07-13
Eddie Hung
Add comment
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2019-07-13
Eddie Hung
Update test with more accurate LUT mask
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2019-07-13
Eddie Hung
duplicate -> clone
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2019-07-13
Eddie Hung
More cleanup
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2019-07-13
Eddie Hung
Cleanup
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2019-07-13
Eddie Hung
Cleanup
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2019-07-13
Eddie Hung
Cleanup
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2019-07-13
Eddie Hung
More cleanup
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2019-07-13
Eddie Hung
Cleanup
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