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yosys.git
2019-12-12
Eddie Hung
Preserve size of $genval$-s in for loops
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2019-12-12
Eddie Hung
Add testcase
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2019-12-11
Eddie Hung
Fix bitwidth mismatch; suppresses iverilog warning
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2019-12-11
David Shah
Merge pull request #1564 from ZirconiumX/intel_housekeeping
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2019-12-10
Dan Ravensloft
synth_intel: a10gx -> arria10gx
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2019-12-10
Dan Ravensloft
synth_intel: cyclone10 -> cyclone10lp
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2019-12-10
Eddie Hung
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapc...
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2019-12-09
Eddie Hung
ice40_opt to restore attributes/name when unwrapping
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2019-12-09
Eddie Hung
ice40_wrapcarry -unwrap to preserve 'src' attribute
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2019-12-09
Eddie Hung
unmap $__ICE40_CARRY_WRAPPER in test
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2019-12-09
Eddie Hung
-unwrap to create $lut not SB_LUT4 for opt_lut
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2019-12-09
Eddie Hung
Sensitive to direct inst of $__ICE40_CARRY_WRAPPER...
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2019-12-09
Eddie Hung
ice40_wrapcarry to really preserve attributes via ...
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2019-12-07
Eddie Hung
Merge pull request #1555 from antmicro/fix-macc-xilinx...
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2019-12-07
Eddie Hung
Drop keep=0 attributes on SB_CARRY
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2019-12-06
Jan Kowalewski
tests: arch: xilinx: Change order of arguments in macc.sh
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2019-12-05
Clifford Wolf
Merge pull request #1551 from whitequark/manual-cell...
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2019-12-05
Eddie Hung
Merge SB_CARRY+SB_LUT4's attributes when creating ...
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2019-12-05
Eddie Hung
Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER
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2019-12-04
whitequark
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, ...
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2019-12-04
whitequark
manual: document behavior of many comb cells more preci...
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2019-12-04
Marcin Kościelnicki
xilinx: Add tristate buffer mapping. (#1528)
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2019-12-04
Marcin Kościelnicki
iopadmap: Refactor and fix tristate buffer mapping...
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2019-12-04
Marcin Kościelnicki
xilinx: Add models for LUTRAM cells. (#1537)
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2019-12-03
Eddie Hung
Check SB_CARRY name also preserved
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2019-12-03
Eddie Hung
$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for...
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2019-12-03
Eddie Hung
ice40_opt to ignore (* keep *) -ed cells
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2019-12-03
Eddie Hung
ice40_wrapcarry to preserve SB_CARRY's attributes
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2019-12-03
Eddie Hung
Add testcase
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2019-12-03
Clifford Wolf
Merge pull request #1524 from pepijndevos/gowindffinit
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2019-12-03
Pepijn de Vos
update test
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2019-12-03
Pepijn de Vos
Use -match-init to not synth contradicting init values
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2019-12-02
David Shah
Merge pull request #1542 from YosysHQ/dave/abc9-loop-fix
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2019-12-02
Clifford Wolf
Merge pull request #1539 from YosysHQ/mwk/ilang-bounds...
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2019-12-01
David Shah
abc9: Fix breaking of SCCs
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2019-11-29
Miodrag Milanović
Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll
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2019-11-29
Marcin Kościelnicki
xilinx: Add missing blackbox cell for BUFPLL.
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2019-11-28
Eddie Hung
Revert "Fold loop"
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2019-11-27
Marcin Kościelnicki
read_ilang: do bounds checking on bit indices
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2019-11-27
Eddie Hung
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_...
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2019-11-27
Clifford Wolf
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr
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2019-11-27
Clifford Wolf
Merge pull request #1534 from YosysHQ/mwk/opt_share-fix
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2019-11-27
Eddie Hung
Merge pull request #1535 from YosysHQ/eddie/write_xaige...
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2019-11-27
Eddie Hung
No need for -abc9
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2019-11-27
Marcin Kościelnicki
opt_share: Fix handling of fine cells.
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2019-11-27
Eddie Hung
latch -> box
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2019-11-27
Eddie Hung
Add citation
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2019-11-27
Eddie Hung
Check for either sign or zero extension for postAdd...
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2019-11-27
Eddie Hung
Remove notes
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2019-11-27
Eddie Hung
Fold loop
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2019-11-27
Eddie Hung
Do not sigmap keep bits inside write_xaiger
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2019-11-27
Eddie Hung
xaiger: do not promote output wires
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2019-11-27
Eddie Hung
Add testcase derived from fastfir_dynamictaps benchmark
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2019-11-26
Marcin Kościelnicki
xilinx: Add simulation models for IOBUF and OBUFT.
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2019-11-25
Marcin Kościelnicki
clkbufmap: Add support for inverters in clock path.
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2019-11-25
Marcin Kościelnicki
xilinx: Use INV instead of LUT1 when applicable
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2019-11-25
Pepijn de Vos
attempt to fix formatting
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2019-11-25
Pepijn de Vos
gowin: add and test dff init values
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2019-11-23
Eddie Hung
Merge pull request #1520 from pietrmar/fix-1463
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2019-11-23
Martin Pietryka
coolrunner2: remove spurious log_pop() call, fixes...
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2019-11-22
Clifford Wolf
Merge pull request #1517 from YosysHQ/clifford/optmem
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2019-11-22
Clifford Wolf
Merge pull request #1515 from YosysHQ/clifford/svastuff
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2019-11-22
Clifford Wolf
Add "opt_mem" pass
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2019-11-22
Clifford Wolf
Add Verific support for SVA nexttime properties
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2019-11-22
Clifford Wolf
Improve handling of verific primitives in "verific...
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2019-11-22
Clifford Wolf
Add Verific SVA support for "always" properties
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2019-11-22
Clifford Wolf
Merge pull request #1511 from YosysHQ/dave/always
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2019-11-22
Marcin Kościelnicki
gowin: Remove show command from tests.
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2019-11-22
Marcin Kościelnicki
gowin: Add missing .gitignore entries
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2019-11-22
David Shah
Update CHANGELOG and README
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2019-11-21
David Shah
sv: Add tests for SV always types
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2019-11-21
David Shah
proc_dlatch: Add error handling for incorrect always_...
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2019-11-21
David Shah
sv: Correct parsing of always_comb, always_ff and alway...
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2019-11-20
Clifford Wolf
Merge pull request #1507 from YosysHQ/clifford/verificfixes
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2019-11-20
Clifford Wolf
Correctly treat empty modules as blackboxes in Verific
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2019-11-20
Clifford Wolf
Do not rename VHDL entities to "entity(impl)" when...
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2019-11-19
Clifford Wolf
Merge pull request #1449 from pepijndevos/gowin
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2019-11-19
Pepijn de Vos
Remove dff init altogether
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2019-11-19
Marcin Kościelnicki
Fix #1462, #1480.
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2019-11-19
Marcin Kościelnicki
xilinx: Add simulation models for MULT18X18* and DSP48A*.
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2019-11-18
David Shah
memory_collect: Copy attr from RTLIL::Memory to cell
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2019-11-18
Pepijn de Vos
add help for nowidelut and abc9 options
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2019-11-18
Clifford Wolf
Merge pull request #1497 from YosysHQ/mwk/extract-fa-fix
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2019-11-18
whitequark
Merge pull request #1494 from whitequark/write_verilog...
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2019-11-18
Marcin Kościelnicki
Fix #1496.
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2019-11-18
whitequark
write_verilog: add -extmem option, to write split memor...
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2019-11-17
Clifford Wolf
Merge pull request #1492 from YosysHQ/dave/wreduce...
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2019-11-16
Pepijn de Vos
Merge branch 'master' of https://github.com/YosysHQ...
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2019-11-15
David Shah
ecp5: Use new autoname pass for better cell/net names
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2019-11-14
David Shah
wreduce: Don't trim zeros or sext when not matching...
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2019-11-14
Clifford Wolf
Merge pull request #1490 from YosysHQ/clifford/autoname
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2019-11-14
Clifford Wolf
Merge pull request #1444 from btut/feature/python_wrapp...
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2019-11-14
Clifford Wolf
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim
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2019-11-14
Clifford Wolf
Merge branch 'makaimann-label-bads-btor'
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2019-11-14
Clifford Wolf
Use cell name for btor bad state props when it is a...
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2019-11-14
Clifford Wolf
Merge branch 'label-bads-btor' of https://github.com...
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2019-11-13
Clifford Wolf
Add "autoname" pass and use it in "synth_ice40"
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2019-11-13
whitequark
Merge pull request #1488 from whitequark/flowmap-fixes
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2019-11-13
Clifford Wolf
Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix
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2019-11-12
Clifford Wolf
Update fsm_detect bugfix
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