yosys.git
2019-09-26 Eddie Hungxilinx_dsp_cascade to also cascade AREG and BREG
2019-09-26 Eddie HungTry recursive pmgen for P cascade
2019-09-26 Eddie HungCombine 'flatten' & 'coarse' labels in synth_ecp5 so...
2019-09-26 Eddie HungTypo
2019-09-26 Eddie HungCREG to check for \keep
2019-09-26 Eddie HungRemove newline
2019-09-26 Eddie Hungselect once
2019-09-26 Eddie HungStop trying to be too smart by prematurely optimising
2019-09-26 Eddie Hungmul2dsp.v slice names
2019-09-26 Eddie HungDo not die if DSP48E1.P has no users (would otherwise...
2019-09-26 Eddie HungReject if (* init *) present
2019-09-26 Eddie HungRemove unnecessary check for A_SIGNED != B_SIGNED;...
2019-09-26 Eddie HungRevert "Remove _TECHMAP_CELLTYPE_ check since all ...
2019-09-26 Eddie HungRevert "No need for $__mul anymore?"
2019-09-26 Eddie HungRework xilinx_dsp postAdd for new wreduce call
2019-09-26 Eddie HungOnly wreduce on t:$add
2019-09-25 Eddie HungRemove _TECHMAP_CELLTYPE_ check since all $mul
2019-09-25 Eddie HungFix memory issue since SigSpec& could be invalidated
2019-09-25 Eddie HungNo need for $__mul anymore?
2019-09-25 Eddie Hungunextend only used in init
2019-09-25 Eddie HungCall 'wreduce' after mul2dsp to avoid unextend()
2019-09-25 Eddie HungOops. Actually use __NAME__ in ABC_DSP48E1 macro
2019-09-24 Eddie HungAdd (* techmap_autopurge *) to abc_unmap.v too
2019-09-24 Eddie Hung"abc_padding" attr for blackbox outputs that were padde...
2019-09-24 Eddie HungForce $inout.out ports to begin with '$' to indicate...
2019-09-24 Eddie HungAdd techmap_autopurge to outputs in abc_map.v too
2019-09-24 Eddie HungRevert "Add a xilinx_finalise pass"
2019-09-24 Eddie HungRevert "Remove (* techmap_autopurge *) from abc_unmap...
2019-09-24 Eddie HungRevert "Vivado does not like zero width port connections"
2019-09-24 Eddie HungVivado does not like zero width port connections
2019-09-24 Eddie HungRemove (* techmap_autopurge *) from abc_unmap.v since...
2019-09-24 Eddie HungAdd a xilinx_finalise pass
2019-09-23 Eddie HungSet [AB]CASCREG to legal values
2019-09-23 Eddie HungComment to explain separating CREG packing
2019-09-23 Eddie HungSeparate out CREG packing into new pattern, to avoid...
2019-09-23 Eddie HungMove log_debug("\n") later
2019-09-23 Eddie HungMove unextend initialisation later
2019-09-23 Eddie HungUse new port() overload once more
2019-09-23 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-09-21 Clifford WolfMerge pull request #1392 from YosysHQ/eddie/fix1391
2019-09-21 Eddie HungHell let's add the original #1381 testcase too
2019-09-21 Eddie HungRevert abc9.cc
2019-09-21 Eddie HungAdd testcase
2019-09-21 Eddie HungTrim mismatched connection to be same (smallest) size
2019-09-21 Eddie HungFix first testcase in #1391
2019-09-20 Eddie HungGrammar
2019-09-20 Eddie HungUse new port/param overload in pmg
2019-09-20 Eddie HungOutput pattern matcher items as log_debug()
2019-09-20 Eddie HungOPMODE is port not param
2019-09-20 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-09-20 Eddie HungDo not run xilinx_dsp_cascadeAB for now
2019-09-20 Eddie HungWIP for xiinx_dsp_cascadeAB
2019-09-20 Eddie HungRun until convergence
2019-09-20 Eddie HungCleanup ice40_dsp.pmg
2019-09-20 Eddie HungCleanup xilinx_dsp
2019-09-20 Eddie HungMore exceptions
2019-09-20 Eddie HungFix signedness bug
2019-09-20 Eddie HungUpdate doc
2019-09-20 Eddie HungAdd a xilinx_dsp_cascade matcher for PCIN -> PCOUT
2019-09-20 Eddie HungAdd an overload for port/param with default value
2019-09-20 Eddie HungRe-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine...
2019-09-20 Eddie HungRevert "Move mul2dsp before wreduce"
2019-09-20 Eddie HungMove mul2dsp before wreduce
2019-09-20 Eddie HungSmall cleanup
2019-09-20 Clifford WolfMerge pull request #1386 from YosysHQ/clifford/fix1360
2019-09-20 Clifford WolfFix handling of read_verilog config in AstModule::repro...
2019-09-20 Clifford WolfUpdate CHANGELOG
2019-09-20 Clifford WolfAdd "add -mod"
2019-09-20 Clifford WolfMerge pull request #1384 from YosysHQ/clifford/fix1381
2019-09-20 Eddie HungDisable support for SB_MAC16 reset since it is async
2019-09-20 Eddie HungSB_MAC16 ffCD to not pack same as ffO
2019-09-20 Eddie HungAdd more complicated macc testcase
2019-09-20 Eddie HungClarify
2019-09-20 Eddie HungUpdate doc for ice40_dsp
2019-09-20 Eddie HungTidy up, fix undriven
2019-09-20 Eddie HungAdd an index
2019-09-20 Eddie Hung$__ABC_REG to have WIDTH parameter
2019-09-20 Eddie HungFix DSP48E1 timing by breaking P path if MREG or PREG
2019-09-20 Eddie HungRevert "Different approach to timing"
2019-09-20 Eddie HungDifferent approach to timing
2019-09-20 Eddie HungFix width of D
2019-09-20 Eddie HungAdd mac.sh and macc_tb.v for testing
2019-09-19 Eddie HungSuppress $anyseq warnings
2019-09-19 Eddie HungUse ID() macro
2019-09-19 Eddie HungUse (* techmap_autopurge *) to suppress techmap warnings
2019-09-19 Eddie HungD is 25 bits not 24 bits wide
2019-09-19 Eddie HungMerge remote-tracking branch 'origin/clifford/fix1381...
2019-09-19 Eddie HungWhen two boxes connect to each other, need not be a...
2019-09-19 Eddie HungRe-enable sign extension for C input
2019-09-19 Eddie Hungsynth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB...
2019-09-19 Eddie HungTidy up synth_ice40, only restrict DSP_B_MINWIDTH=2
2019-09-19 Eddie HungDo not perform width-checks for DSP48E1 which is much...
2019-09-19 Eddie HungRemove TODO as check should not be necessary
2019-09-19 Eddie HungRevert index to select
2019-09-19 Eddie HungCleanup xilinx_dsp too
2019-09-19 Eddie HungRefactor ce{mux,pol} -> hold{mux,pol}
2019-09-19 Eddie HungAdd HOLD/RST support for SB_MAC16
2019-09-19 Eddie HungAdd support for SB_MAC16 CD and H registers
2019-09-19 Eddie HungRefactor ice40_dsp.pmg
2019-09-19 Eddie HungAdd more entries
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