yosys.git
2019-06-27 Eddie HungExtraneous newline
2019-06-27 Eddie HungRemove noise from ice40/cells_sim.v
2019-06-27 Eddie HungRefactor for one "abc_carry" attribute on module
2019-06-27 Eddie HungMerge branch 'xaig' of github.com:YosysHQ/yosys into...
2019-06-27 Eddie HungDo not use Module::remove() iterator version
2019-06-27 Eddie HungRemove redundant doc
2019-06-27 Eddie HungRemove &retime when abc9 -fast
2019-06-27 Eddie HungCleanup abc9.cc
2019-06-27 Eddie HungUndo iterator based Module::remove() for cells, as...
2019-06-27 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-27 Eddie HungMerge pull request #1139 from YosysHQ/dave/check-sim...
2019-06-27 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-27 Eddie HungGrr
2019-06-27 Eddie HungCapitalisation
2019-06-27 Eddie HungMake CHANGELOG clearer
2019-06-27 Eddie HungMerge pull request #1143 from YosysHQ/clifford/fix1135
2019-06-27 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-27 Eddie HungAdd warning if synth_xilinx -abc9 with family != xc7
2019-06-27 Eddie HungRemove unneeded include
2019-06-27 Eddie HungMerge origin/master
2019-06-27 Eddie HungAdd simcells.v, simlib.v, and some output
2019-06-27 Eddie HungAdd #1135 testcase
2019-06-27 Eddie Hungsynth_xilinx -arch -> -family, consistent with older...
2019-06-27 Eddie HungMerge pull request #1142 from YosysHQ/clifford/fix1132
2019-06-27 Eddie HungMerge pull request #1138 from YosysHQ/koriakin/xc7nocar...
2019-06-27 Eddie HungCopy tests from eddie/fix1132
2019-06-27 Clifford WolfAdd "pmux2shiftx -norange", fixes #1135
2019-06-27 Clifford WolfFix handling of partial covers in muxcover, fixes ...
2019-06-27 Eddie HungFix spacing
2019-06-27 Eddie HungImprove debugging message for comb loops
2019-06-27 Eddie HungAdd WE to ECP5 dist RAM's abc_scc_break too
2019-06-27 Eddie HungUpdate comment on boxes
2019-06-27 Eddie HungAdd "WE" to dist RAM's abc_scc_break
2019-06-27 Eddie HungSupport more than one port in the abc_scc_break attr
2019-06-27 Eddie HungAdd write_xaiger into CHANGELOG
2019-06-26 Eddie HungMerge branch 'koriakin/xc7nocarrymux' into xaig
2019-06-26 Eddie HungGrrr
2019-06-26 David Shahtests: Check that Icarus can parse arch sim models
2019-06-26 Eddie HungRemove unused var
2019-06-26 Eddie HungAdd _nowide variants of LUT libraries in -nowidelut...
2019-06-26 Eddie HungMerge branch 'xaig' of github.com:YosysHQ/yosys into...
2019-06-26 Eddie HungMerge branch 'koriakin/xc7nocarrymux' into xaig
2019-06-26 Eddie HungFix spacing
2019-06-26 Eddie HungMerge branch 'koriakin/xc7nocarrymux' into xaig
2019-06-26 Eddie HungOops. Actually use nocarry flag as spotted by @koriakin
2019-06-26 Clifford WolfMerge pull request #1137 from mmicko/cell_sim_fix
2019-06-26 Eddie HungMerge branch 'koriakin/xc7nocarrymux' into xaig
2019-06-26 Miodrag MilanovicSimulation model verilog fix
2019-06-26 Eddie Hungsynth_ecp5 rename -nomux to -nowidelut, but preserve...
2019-06-26 Eddie HungMerge branch 'xc7nocarrymux' of https://github.com...
2019-06-26 Clifford WolfImprove opt_clean handling of unused public wires
2019-06-26 Eddie HungMerge pull request #1136 from YosysHQ/xaig_ice40_wire_del
2019-06-26 Clifford WolfImprove BTOR2 handling of undriven wires
2019-06-26 David Shahabc9: Add wire delays to synth_ice40
2019-06-26 Clifford WolfFix segfault on failed VERILOG_FRONTEND::const2ast...
2019-06-26 Clifford WolfDo not clean up buffer cells with "keep" attribute...
2019-06-26 Clifford WolfEscape scope names starting with dollar sign in smtio.py
2019-06-26 whitequarkAdd more ECP5 Diamond flip-flops.
2019-06-25 Eddie HungMissing muxpack.o in Makefile
2019-06-25 Eddie HungRealistic delays for RAM32X1D too
2019-06-25 Eddie HungAdd RAM32X1D box info
2019-06-25 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-25 Eddie HungAdd testcase from #335, fixed by #1130
2019-06-25 Clifford WolfMerge pull request #1130 from YosysHQ/eddie/fix710
2019-06-25 Eddie HungFix spacing
2019-06-25 Eddie HungMove only one consumer check outside of while loop
2019-06-25 Eddie HungMerge pull request #1129 from YosysHQ/eddie/ram32x1d
2019-06-25 Clifford WolfMerge pull request #1075 from YosysHQ/eddie/muxpack
2019-06-25 Eddie Hungnullptr check
2019-06-25 Eddie HungUse LUT delays for dist RAM delays
2019-06-25 Eddie HungFix for abc_scc_break is bus
2019-06-25 Eddie HungMore meaningful error message
2019-06-25 Eddie HungRe-enable dist RAM boxes for ECP5
2019-06-25 Eddie HungRevert "Re-enable dist RAM boxes for ECP5"
2019-06-25 Eddie HungDo not use log_id as it strips \\, also fix scc for...
2019-06-25 Eddie HungRe-enable dist RAM boxes for ECP5
2019-06-25 Eddie HungAdd Xilinx dist RAM as comb boxes
2019-06-25 Eddie HungFix abc9's scc breaker, also break on abc_scc_break...
2019-06-25 Eddie HungAdd tests/various/abc9.{v,ys} with SCC test
2019-06-25 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-25 Eddie HungWalk through as many muxes as exist for rd_en
2019-06-25 Eddie HungAdd test
2019-06-24 Eddie HungAdd RAM32X1D support
2019-06-24 Clifford WolfMerge pull request #1124 from mmicko/json_ports
2019-06-22 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-06-22 Eddie HungAdd comments to ecp5 box
2019-06-22 Eddie HungAdd comment to xc7 box
2019-06-22 Eddie HungFix and cleanup ice40 boxes for carry in/out
2019-06-22 Eddie HungCarry in/out box ordering now move to end, not swap...
2019-06-22 Eddie HungRemove DFF and RAMD box info for now
2019-06-22 Eddie HungMerge branch 'master' into xaig
2019-06-22 Eddie HungAdd 'muxcover -dmux=<cost>' and '-nopartial' to CHANGELOG
2019-06-22 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-22 Eddie HungFix CHANGELOG
2019-06-22 Eddie HungReduce log_debug spam in parse_xaiger()
2019-06-22 Eddie HungDo not rename non LUT cells in abc9
2019-06-22 Eddie HungReplace assert with error message
2019-06-22 Eddie HungAdd log_push()/log_pop() inside write_xaiger
2019-06-22 Eddie HungMerge pull request #1108 from YosysHQ/clifford/fix1091
2019-06-21 Eddie HungOne more workaround for gcc-4.8
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