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yosys.git
2019-12-18
Marcin Kościelnicki
xilinx: Improve flip-flop handling.
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2019-12-18
Clifford Wolf
Send people to symbioticeda.com instead of verific.com
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2019-12-17
Eddie Hung
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
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2019-12-17
Eddie Hung
Merge pull request #1521 from dh73/diego/memattr
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2019-12-17
Eddie Hung
Enforce non-existence
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2019-12-16
Eddie Hung
Update doc
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2019-12-16
Eddie Hung
Add another test
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2019-12-16
Eddie Hung
More sloppiness, thanks @dh73 for spotting
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2019-12-16
Eddie Hung
Accidentally commented out tests
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2019-12-16
Eddie Hung
Add unconditional match blocks for force RAM
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2019-12-16
Eddie Hung
Oops
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2019-12-16
Eddie Hung
Merge blockram tests
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2019-12-16
Eddie Hung
Update xc7/xcu bram rules
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2019-12-16
Eddie Hung
Implement 'attributes' grammar
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2019-12-16
Eddie Hung
Merge branch 'diego/memattr' of https://github.com...
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2019-12-16
Eddie Hung
Merge branch 'eddie/xilinx_lutram' of github.com:YosysH...
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2019-12-16
Eddie Hung
Populate DID/DOD even if unused
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2019-12-16
Eddie Hung
Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q
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2019-12-16
Diego H
Fixing compiler warning/issues. Moving test script...
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2019-12-16
Diego H
Removing fixed attribute value to !ramstyle rules
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2019-12-16
Diego H
Merging attribute rules into a single match block;...
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2019-12-16
Eddie Hung
Merge pull request #1575 from rodrigomelo9/master
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2019-12-16
Eddie Hung
Merge pull request #1577 from gromero/for-yosys
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2019-12-16
Eddie Hung
Merge pull request #1578 from noopwafel/eqneq-debug
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2019-12-15
Alyssa Milburn
Fix opt_expr.eqneq.cmpzero debug print
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2019-12-13
Diego H
Refactoring memory attribute matching based on IEEE...
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2019-12-13
Eddie Hung
Merge pull request #1533 from dh73/bram_xilinx
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2019-12-13
Eddie Hung
Disable RAM16X1D test
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2019-12-13
Eddie Hung
Disable RAM16X1D match rule; carry-over from LUT4 arches
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2019-12-13
Eddie Hung
RAM64M8 to also have [5:0] for address
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2019-12-13
Diego H
Renaming BRAM memory tests for the sake of uniformity
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2019-12-13
Rodrigo Alejandro...
Fixed some missing "verilog_" in documentation
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2019-12-13
Eddie Hung
Remove extraneous synth_xilinx call
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2019-12-13
Eddie Hung
Add tests for these new models
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2019-12-13
Eddie Hung
Add RAM32X6SDP and RAM64X3SDP modes
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2019-12-13
Eddie Hung
Fix RAM64M model to have 6 bit address bus
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2019-12-13
Eddie Hung
Add #1460 testcase
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2019-12-13
Eddie Hung
Add memory rules for RAM16X1D, RAM32M, RAM64M
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2019-12-13
Eddie Hung
Rename memory tests to lutram, add more xilinx tests
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2019-12-12
Diego H
Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB3...
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2019-12-12
Eddie Hung
abc9_map.v: fix Xilinx LUTRAM
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2019-12-12
Diego H
Adding a note (TODO) in the memory_params.ys check...
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2019-12-12
Diego H
Updating RAMB36E1 thresholds. Adding test for both...
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2019-12-12
Diego H
Merge https://github.com/YosysHQ/yosys into bram_xilinx
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2019-12-12
Eddie Hung
Update README.md :: abc_ -> abc9_
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2019-12-11
Eddie Hung
Fix bitwidth mismatch; suppresses iverilog warning
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2019-12-11
Gustavo Romero
manual: Fix text in Abstract section
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2019-12-11
David Shah
Merge pull request #1564 from ZirconiumX/intel_housekeeping
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2019-12-10
Dan Ravensloft
synth_intel: a10gx -> arria10gx
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2019-12-10
Dan Ravensloft
synth_intel: cyclone10 -> cyclone10lp
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2019-12-10
Eddie Hung
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapc...
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2019-12-09
Eddie Hung
ice40_opt to restore attributes/name when unwrapping
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2019-12-09
Eddie Hung
ice40_wrapcarry -unwrap to preserve 'src' attribute
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2019-12-09
Eddie Hung
unmap $__ICE40_CARRY_WRAPPER in test
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2019-12-09
Eddie Hung
-unwrap to create $lut not SB_LUT4 for opt_lut
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2019-12-09
Eddie Hung
Sensitive to direct inst of $__ICE40_CARRY_WRAPPER...
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2019-12-09
Eddie Hung
ice40_wrapcarry to really preserve attributes via ...
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2019-12-07
Eddie Hung
Merge pull request #1555 from antmicro/fix-macc-xilinx...
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2019-12-07
Eddie Hung
Drop keep=0 attributes on SB_CARRY
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2019-12-06
Jan Kowalewski
tests: arch: xilinx: Change order of arguments in macc.sh
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2019-12-05
Clifford Wolf
Merge pull request #1551 from whitequark/manual-cell...
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2019-12-05
Eddie Hung
Merge SB_CARRY+SB_LUT4's attributes when creating ...
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2019-12-05
Eddie Hung
Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER
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2019-12-04
whitequark
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, ...
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2019-12-04
whitequark
manual: document behavior of many comb cells more preci...
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2019-12-04
Marcin Kościelnicki
xilinx: Add tristate buffer mapping. (#1528)
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2019-12-04
Marcin Kościelnicki
iopadmap: Refactor and fix tristate buffer mapping...
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2019-12-04
Marcin Kościelnicki
xilinx: Add models for LUTRAM cells. (#1537)
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2019-12-03
Eddie Hung
Check SB_CARRY name also preserved
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2019-12-03
Eddie Hung
$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for...
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2019-12-03
Eddie Hung
ice40_opt to ignore (* keep *) -ed cells
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2019-12-03
Eddie Hung
ice40_wrapcarry to preserve SB_CARRY's attributes
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2019-12-03
Eddie Hung
Add testcase
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2019-12-03
Clifford Wolf
Merge pull request #1524 from pepijndevos/gowindffinit
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2019-12-03
Pepijn de Vos
update test
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2019-12-03
Pepijn de Vos
Use -match-init to not synth contradicting init values
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2019-12-02
David Shah
Merge pull request #1542 from YosysHQ/dave/abc9-loop-fix
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2019-12-02
Clifford Wolf
Merge pull request #1539 from YosysHQ/mwk/ilang-bounds...
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2019-12-01
David Shah
abc9: Fix breaking of SCCs
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2019-11-29
Miodrag Milanović
Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll
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2019-11-29
Marcin Kościelnicki
xilinx: Add missing blackbox cell for BUFPLL.
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2019-11-28
Eddie Hung
Revert "Fold loop"
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2019-11-27
Marcin Kościelnicki
read_ilang: do bounds checking on bit indices
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2019-11-27
Diego H
Adjusting Vivado's BRAM min bits threshold for RAMB18E1
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2019-11-27
Eddie Hung
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_...
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2019-11-27
Clifford Wolf
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr
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2019-11-27
Clifford Wolf
Merge pull request #1534 from YosysHQ/mwk/opt_share-fix
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2019-11-27
Eddie Hung
Merge pull request #1535 from YosysHQ/eddie/write_xaige...
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2019-11-27
Eddie Hung
No need for -abc9
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2019-11-27
Marcin Kościelnicki
opt_share: Fix handling of fine cells.
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2019-11-27
Eddie Hung
latch -> box
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2019-11-27
Eddie Hung
Add citation
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2019-11-27
Eddie Hung
Check for either sign or zero extension for postAdd...
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2019-11-27
Eddie Hung
Remove notes
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2019-11-27
Eddie Hung
Fold loop
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2019-11-27
Eddie Hung
Do not sigmap keep bits inside write_xaiger
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2019-11-27
Eddie Hung
xaiger: do not promote output wires
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2019-11-27
Eddie Hung
Add testcase derived from fastfir_dynamictaps benchmark
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2019-11-26
Marcin Kościelnicki
xilinx: Add simulation models for IOBUF and OBUFT.
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2019-11-25
Marcin Kościelnicki
clkbufmap: Add support for inverters in clock path.
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