yosys.git
2016-08-09 Clifford WolfAdded "attrmap" command
2016-08-09 Clifford WolfAdded log_const() API
2016-08-09 Clifford WolfAdded "attrmvcp" pass
2016-08-08 Yury GribovUse /proc/self/exe on Cygwin as well.
2016-08-08 Clifford WolfUndo "preserve wire attributes in iopadmap" change...
2016-08-06 Clifford WolfAdded "test_autotb -seed" (and "autotest.sh -S")
2016-08-06 Clifford Wolfpreserve wire attributes in iopadmap
2016-08-06 Clifford WolfFixed bug in parsing real constants
2016-08-02 Clifford WolfAdded "insbuf" command
2016-07-30 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-07-30 Clifford WolfAdded "write_verilog -defparam"
2016-07-30 Clifford WolfAdded "write_verilog -nodec -nostr"
2016-07-27 Clifford WolfAdded $initstate support to smtbmc flow
2016-07-27 Clifford WolfAdded SatGen support for $anyconst
2016-07-27 Clifford WolfRemoved $predict support from SatGen
2016-07-27 Clifford WolfAdded $anyconst and $aconst
2016-07-27 Clifford WolfAdded "read_verilog -dump_rtlil"
2016-07-25 Clifford WolfRenamed AbstractCellEdgesDatabase::add_cell() to add_ed...
2016-07-25 Clifford WolfFixed a verilog parser memory leak
2016-07-25 Clifford WolfFixed parsing of empty positional cell ports
2016-07-24 Clifford WolfImprovements in CellEdgesDatabase
2016-07-24 Clifford WolfAdded CellEdgesDatabase API
2016-07-24 Clifford WolfMoved SatHelper::setup_init() code to SatHelper::setup()
2016-07-23 Clifford WolfAdded $initstate support to "sat" command
2016-07-23 Clifford WolfNo tristate warning message for "read_verilog -lib"
2016-07-22 Clifford WolfAdded satgen initstate support
2016-07-21 Clifford WolfUsing $initstate in "initial assume" and "initial assert"
2016-07-21 Clifford WolfAdded $initstate cell type and vlog function
2016-07-21 Clifford WolfAfter reading the SV spec, using non-standard predict...
2016-07-13 Clifford WolfAdded basic support for $expect cells
2016-07-13 Clifford WolfAdded examples/smtbmc
2016-07-13 Clifford WolfMerge pull request #191 from whitequark/json-module...
2016-07-13 Clifford WolfMerge pull request #193 from azonenberg/master
2016-07-12 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-07-12 Clifford WolfMinor bugfix in FSM reset state detection
2016-07-12 whitequarkwrite_json: also write module attributes.
2016-07-12 Andrew ZonenbergAdded GP_DAC cell
2016-07-12 Andrew ZonenbergRemoved VOUT port of GP_BANDGAP
2016-07-12 Andrew ZonenbergRemoved splitnets in prep for new gp4par parser
2016-07-11 Clifford WolfYosys-smtbmc: Support for hierarchical VCD dumping
2016-07-11 Clifford WolfMoved smt2 yosys info parsing from smtbmc.py to smtio.py
2016-07-11 Clifford WolfAdded "prep -auto-top" and "synth -auto-top"
2016-07-10 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-07-10 Clifford WolfMerge pull request #189 from whitequark/master
2016-07-10 Clifford WolfSupport for hierarchical designs in smt2 back-end
2016-07-10 whitequarkgreenpak4: add GP_COUNT{8,14}_ADV cells.
2016-07-09 Clifford WolfFurther improved fsm_detect output, attempt to detect...
2016-07-09 Clifford WolfAdded printing of some warning messages to fsm_detect
2016-07-08 Clifford WolfAdded warning about adding fsm_encoding attributes...
2016-07-08 Clifford WolfMinor fixes in ice40_ff* passes for sloppy SB_DFF insta...
2016-07-08 Clifford WolfFixed mem assignment in left-hand-side concatenation
2016-07-08 Clifford WolfMerge branch 'eddiehung-vtr'
2016-07-08 Clifford WolfRestored blif "-true - .." behavior, use "-true + ...
2016-07-08 Clifford WolfIn BLIF, a .names without entries already always outputs 0
2016-07-08 Clifford WolfUndo eddiehung-vtr Makefile changes
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-07-02 Clifford WolfFixed autotest.sh handling of `timescale
2016-07-01 Clifford WolfMerge branch 'assert-limit'
2016-07-01 Clifford WolfReplaced "select -assert-limit" with -assert-max and...
2016-07-01 eshellkoAdded 'assert-limit' option for 'select' command
2016-06-30 Clifford WolfImproved ice40_ffinit error reporting
2016-06-21 Clifford WolfMerge pull request #181 from rubund/input_logic_allowed
2016-06-20 Ruben UndheimAllow defining input ports as "input logic" in SystemVe...
2016-06-19 Clifford WolfBugfix in "abc -script" handling
2016-06-19 Clifford WolfMerge branch 'sv_packages' of https://github.com/rubund...
2016-06-19 Clifford WolfAdded "deminout"
2016-06-18 Ruben UndheimA few modifications after pull request comments
2016-06-18 Clifford WolfAdded "read_blif -sop"
2016-06-18 Clifford WolfAdded $sop support to BLIF back-end
2016-06-18 Ruben UndheimAdded support for SystemVerilog packages with localpara...
2016-06-17 Clifford WolfAdded "dc2" to default ABC scripts
2016-06-17 Clifford WolfFixed init issue in mem2reg_test2 test case
2016-06-17 Clifford WolfAdded "abc -I <num> -P <num>"
2016-06-17 Clifford WolfAdded $sop SAT model
2016-06-17 Clifford WolfImproved support for $sop cells
2016-06-17 Clifford WolfAdded $sop cell type and "abc -sop"
2016-06-17 Clifford WolfUpdated ABC to hg rev b5df6e2b76f0
2016-06-09 Clifford WolfAdded "nlutmap -assert"
2016-06-08 Clifford WolfDo not run "wreduce" in "prep -ifx"
2016-06-06 Clifford WolfAdded "proc_mux -ifx"
2016-06-03 Clifford WolfAdded "setundef -init"
2016-06-02 Clifford WolfFix all undef-muxes in dlatch input cone
2016-06-01 Clifford WolfAvoid creating undef-muxes when inferring latches in...
2016-05-29 Clifford WolfAdded opt_expr support for div/mod by power-of-two
2016-05-27 Clifford WolfFixed procedural assignments to non-unique lvalues...
2016-05-27 Clifford WolfFixed access-after-delete bug in mem2reg code
2016-05-27 Clifford Wolffixed typos in error messages
2016-05-27 Clifford WolfFixed "scc" for cells that have feedback singals _and_...
2016-05-22 Clifford WolfMerge pull request #172 from zeldin/deterministic_hierarchy
2016-05-22 Marcus ComstedtMade the expansion order of hierarchy deterministic
2016-05-20 Clifford WolfSome fixes in tests/asicworld/*_tb.v
2016-05-20 Clifford WolfImprovements and fixes in autotest.sh script and test_a...
2016-05-20 Clifford WolfMerge branch 'master' of https://github.com/Kmanfi...
2016-05-20 Clifford WolfAlso escape "=" in spice output
2016-05-20 Clifford WolfSmall improvements in Verilog front-end docs
2016-05-19 Kaj TuomiClose opened dump file.
2016-05-19 Kaj TuomiFix for Modelsim transcript line warp issue #164
2016-05-14 Clifford WolfDon't sign-extend memory bram initialization data
2016-05-14 Clifford WolfAdded missing "#define HASHLIB_H"
2016-05-14 Clifford WolfMinor presentation fixes
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