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litex.git
2012-06-12
Sebastien Bourdeauducq
actorlib: ASMI sequential reader
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2012-06-12
Sebastien Bourdeauducq
examples/dataflow/dma: refactor
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2012-06-12
Sebastien Bourdeauducq
fix SimActor get_fragment
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2012-06-12
Sebastien Bourdeauducq
Reorganize examples folder
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2012-06-12
Sebastien Bourdeauducq
PureSimulable
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2012-06-12
Sebastien Bourdeauducq
ASMI simulation models
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2012-06-10
Sebastien Bourdeauducq
wishbone: base TargetModel class
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2012-06-10
Sebastien Bourdeauducq
bus/wishbone: target model
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2012-06-10
Sebastien Bourdeauducq
bus/wishbone/Tap: remove ack feature
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2012-06-08
Sebastien Bourdeauducq
examples/dataflow: only import nx when needed
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2012-06-08
Sebastien Bourdeauducq
flow/network: refactor graph
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2012-06-08
Sebastien Bourdeauducq
flow/ala: fix typo
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2012-06-08
Sebastien Bourdeauducq
actorlib: WB writer simulation OK
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2012-06-08
Sebastien Bourdeauducq
actorlib: WB reader simulation OK
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2012-06-08
Sebastien Bourdeauducq
Use super() instead of calling parent constructors...
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2012-06-08
Sebastien Bourdeauducq
actorlib/sim: use set instead of list to represent...
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2012-06-08
Sebastien Bourdeauducq
actorlib: generator-based generic simulation actor
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2012-06-08
Sebastien Bourdeauducq
sim: multiread/multiwrite
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2012-06-08
Sebastien Bourdeauducq
corelogic/record: better repr
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2012-06-08
Sebastien Bourdeauducq
examples/fir: print Verilog source
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2012-06-07
Sebastien Bourdeauducq
examples/fir: plot input and output signals
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2012-06-07
Sebastien Bourdeauducq
flow: generic parameter passing to Actor from sequentia...
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2012-06-07
Sebastien Bourdeauducq
flow: fix actor repr
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2012-06-07
Sebastien Bourdeauducq
flow: refactor scheduling models
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2012-05-21
Sebastien Bourdeauducq
bank/description: pad unaligned multi-word registers...
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2012-05-21
Sebastien Bourdeauducq
Add LICENSE file
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2012-05-15
Sebastien Bourdeauducq
bus/wishbone2asmi: fix cache tag size
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2012-05-15
Sebastien Bourdeauducq
asmi: dat_wm high to disable data write
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2012-04-30
Sebastien Bourdeauducq
bus/asmibus/hub: hack to prevent comb loops
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2012-04-30
Sebastien Bourdeauducq
fhdl/verilog: add option to display which comb blocks...
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2012-04-30
Sebastien Bourdeauducq
sim: pass extra keyword arguments to Verilog converter
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2012-04-08
Sebastien Bourdeauducq
fhdl: support len() on signals
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2012-04-06
Sebastien Bourdeauducq
bank/csrgen: allow specifying existing CSR interface
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2012-04-02
Sebastien Bourdeauducq
fhdl: phase out pads
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2012-04-02
Sebastien Bourdeauducq
vpi: delete merged Icarus Verilog patch
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2012-04-02
Sebastien Bourdeauducq
fhdl/verilog: do not attempt to initialize instance...
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2012-04-01
Sebastien Bourdeauducq
bus/dfi: reset active low signals to 1
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2012-04-01
Sebastien Bourdeauducq
sim/proxy: support lists
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2012-04-01
Sebastien Bourdeauducq
fhdl/verilog: initialize internal read-only signals...
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2012-03-31
Sebastien Bourdeauducq
corelogic/roundrobin: handle correctly special case...
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2012-03-30
Sebastien Bourdeauducq
bus/asmicon: initiator
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2012-03-30
Sebastien Bourdeauducq
sim: proxy
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2012-03-23
Sebastien Bourdeauducq
Update copyright notices
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2012-03-18
Sebastien Bourdeauducq
corelogic/fsm: typo
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2012-03-17
Sebastien Bourdeauducq
corelogic/fsm: delayed enters
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2012-03-16
Sebastien Bourdeauducq
corelogic/roundrobin: CE switching
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2012-03-15
Sebastien Bourdeauducq
corelogic: convert timeline to function and move to...
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2012-03-14
Sebastien Bourdeauducq
bus/asmibus/hub: require finalization before get_slots
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2012-03-14
Sebastien Bourdeauducq
fhdl: export log2_int
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2012-03-10
Alain Péteut
setup.py: simplify
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2012-03-10
Sebastien Bourdeauducq
doc: more examples and comments
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2012-03-10
Sebastien Bourdeauducq
doc: cosmetic changes (thanks sh4rm4 for reporting...
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2012-03-09
Sebastien Bourdeauducq
doc: use script font
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2012-03-09
Sebastien Bourdeauducq
doc: simulation
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2012-03-09
Sebastien Bourdeauducq
doc: cosmetic changes (thanks rofl0r for reporting...
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2012-03-09
Sebastien Bourdeauducq
doc: add logo
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2012-03-09
Sebastien Bourdeauducq
doc: switch to sphinx
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2012-03-08
Sebastien Bourdeauducq
examples: FIR filter simulation
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2012-03-08
Sebastien Bourdeauducq
fhdl: handle negative constants correctly
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2012-03-08
Sebastien Bourdeauducq
examples: remove outdated wb_intercon simulation
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2012-03-08
Sebastien Bourdeauducq
vpi: support extra include directories
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2012-03-08
Sebastien Bourdeauducq
gitignore: update
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2012-03-08
Sebastien Bourdeauducq
bus: generic transaction model
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2012-03-08
Sebastien Bourdeauducq
vpi: patch for Icarus Verilog
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2012-03-08
Sebastien Bourdeauducq
examples: small cleanup
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2012-03-08
Sebastien Bourdeauducq
sim: fix zero encoding
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2012-03-08
Sebastien Bourdeauducq
sim: fix message debug formatting
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2012-03-06
Sebastien Bourdeauducq
sim: make initialization cycle optional (selectable...
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2012-03-06
Sebastien Bourdeauducq
sim: memory access
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2012-03-06
Sebastien Bourdeauducq
fhdl: register memory objects with namespace
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2012-03-06
Sebastien Bourdeauducq
sim: support for signed numbers
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2012-03-06
Sebastien Bourdeauducq
fhdl/verilog: fix signed constant conversion
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2012-03-06
Sebastien Bourdeauducq
vpi: install target
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2012-03-06
Sebastien Bourdeauducq
sim: VCD generation
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2012-03-06
Sebastien Bourdeauducq
sim: clean startup/shutdown
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2012-03-06
Sebastien Bourdeauducq
sim: remove temporary files and socket
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2012-03-06
Sebastien Bourdeauducq
fhdl/namer: do not reference objects with __del__ metho...
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2012-03-06
Sebastien Bourdeauducq
sim: remove default sockaddr
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2012-03-06
Sebastien Bourdeauducq
fhdl: add simulation functions in fragment
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2012-03-05
Sebastien Bourdeauducq
sim: basic functionality working
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2012-03-05
Sebastien Bourdeauducq
sim: signal writes working
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2012-03-04
Sebastien Bourdeauducq
sim: cleanups
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2012-03-04
Sebastien Bourdeauducq
sim: signal reads working
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2012-03-04
Sebastien Bourdeauducq
sim: compile VPI module
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2012-03-04
Sebastien Bourdeauducq
sim: two way IPC working
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2012-03-03
Sebastien Bourdeauducq
sim: IPC module (lacks str/int encoding)
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2012-02-29
Sebastien Bourdeauducq
README: clarify license
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2012-02-19
Sebastien Bourdeauducq
bus/dfi: fix multiphase naming
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2012-02-18
Sebastien Bourdeauducq
bank/csrgen: fix RE generation
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2012-02-17
Sebastien Bourdeauducq
bank: add RE signal for registers made of fields
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2012-02-17
Sebastien Bourdeauducq
bus: add interconnect statements function
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2012-02-17
Sebastien Bourdeauducq
fhdl: check we pass BV to signals
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2012-02-17
Sebastien Bourdeauducq
fhdl/verilog: properly connect instance inouts
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2012-02-16
Sebastien Bourdeauducq
fhdl: support forwarding of bidirectional signals from...
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2012-02-15
Sebastien Bourdeauducq
bus/dfi: filter signals by direction
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2012-02-15
Sebastien Bourdeauducq
bank: omit device write register when access_bus==READ_...
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2012-02-15
Sebastien Bourdeauducq
bus: add DFI
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2012-02-15
Sebastien Bourdeauducq
bank/csrgen: use new bus API
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2012-02-15
Sebastien Bourdeauducq
bus: fix simple interconnect
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2012-02-15
Sebastien Bourdeauducq
bus: simplify and cleanup
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