yosys.git
2019-04-20 Eddie HungMerge remote-tracking branch 'origin/pmux2shiftx' into...
2019-04-20 Eddie HungMerge remote-tracking branch 'origin' into xc7srl
2019-04-20 Clifford WolfMerge pull request #942 from YosysHQ/clifford/fix931
2019-04-19 Clifford WolfImprove "show" handling of 0/1/X/Z padding
2019-04-19 Clifford WolfChange "ne" to "neq" in btor2 output
2019-04-19 Clifford WolfAdd tests/aiger/.gitignore
2019-04-19 Eddie HungSpelling fixes
2019-04-18 Clifford WolfUpdate to ABC 3709744
2019-04-18 Eddie HungMerge pull request #917 from YosysHQ/eddie/fix_retime
2019-04-18 Eddie HungFix abc's remap_name to not ignore [^0-9] when extracti...
2019-04-18 Eddie HungABC to call retime all the time
2019-04-18 Eddie HungRevert "synth_* with -retime option now calls abc with...
2019-04-18 Eddie HungMerge branch 'master' into eddie/fix_retime
2019-04-18 Clifford WolfImprove proc full_case detection and handling, fixes...
2019-04-17 Clifford WolfUpdate to ABC d1b6413
2019-04-16 Eddie HungMerge pull request #939 from YosysHQ/revert895
2019-04-16 Eddie HungRevert #895
2019-04-16 Eddie HungMerge pull request #937 from YosysHQ/revert-932-eddie...
2019-04-16 Eddie HungRevert "Recognise default entry in case even if all...
2019-04-15 Eddie HungMerge pull request #936 from YosysHQ/README-fix-quotes
2019-04-15 whitequarkREADME: fix some incorrect quoting.
2019-04-12 Eddie HungMerge pull request #928 from litghost/add_xc7_sim_models
2019-04-12 Keith RothmanRemove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
2019-04-12 Clifford WolfMerge pull request #933 from dh73/master
2019-04-12 Clifford WolfMerge pull request #932 from YosysHQ/eddie/fixdlatch
2019-04-12 DiegoFixing issues in CycloneV cell sim
2019-04-11 Eddie HungFix ordering of when to insert zero index
2019-04-11 Eddie HungMore unused
2019-04-11 Eddie HungRemove unused
2019-04-11 Eddie HungFixes
2019-04-11 Eddie HungWIP
2019-04-11 Eddie HungSpelling fixes
2019-04-11 Eddie HungAdd default entry to testcase
2019-04-11 Eddie HungRecognise default entry in case even if all cases cover...
2019-04-10 Eddie Hungsynth_* with -retime option now calls abc with -D 1...
2019-04-10 Eddie HungRevert "abc -dff now implies "-D 0" otherwise retiming...
2019-04-10 Eddie HungRevert ""&nf -D 0" fails => use "-D 1" instead"
2019-04-10 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-04-09 Keith RothmanFix LUT6_2 definition.
2019-04-09 Keith RothmanAdd additional cells sim models for core 7-series prima...
2019-04-08 Eddie HungFix a few typos
2019-04-08 Eddie Hung$_XILINX_SHREG_ to preserve src attribute
2019-04-08 Eddie HungUpdate CHANGELOG
2019-04-08 Eddie HungMerge branch 'undo_pr895' into xc7srl
2019-04-08 Eddie HungUndo #895 by instead setting an attribute
2019-04-08 Eddie HungCope with undoing #895
2019-04-08 Clifford WolfMerge pull request #919 from YosysHQ/multiport_transp
2019-04-08 Eddie HungRevert "Remove handling for $pmux, since #895"
2019-04-07 David Shahmemory_bram: Fix multiport make_transp
2019-04-06 Eddie HungCall shregmap twice -- once for variable, another for...
2019-04-05 Eddie HungMerge branch 'eddie/fix_retime' into xc7srl
2019-04-05 Eddie HungAdd retime test
2019-04-05 Eddie HungFix S0 -> S1
2019-04-05 Eddie HungMove dffinit til after abc
2019-04-05 Eddie HungMerge branch 'eddie/fix_retime' into xc7srl
2019-04-05 Eddie HungMove techamp t:$_DFF_?N? to before abc call
2019-04-05 Eddie HungRetry
2019-04-05 Eddie Hung"&nf -D 0" fails => use "-D 1" instead
2019-04-05 Eddie HungResolve @daveshah1 comment, update synth_xilinx help
2019-04-05 Eddie Hungsynth_xilinx to techmap FFs after abc call, otherwise...
2019-04-05 Eddie Hungabc -dff now implies "-D 0" otherwise retiming doesn...
2019-04-05 Eddie Hungtechmap inside map_cells stage
2019-04-05 Clifford WolfAdd "read_ilang -lib"
2019-04-04 Clifford WolfAdded missing argument checking to "mutate" command
2019-04-04 Eddie HungMerge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 Eddie HungMissing techmap entry in help
2019-04-04 Eddie HungUse soft-logic, not LUT3 instantiation
2019-04-04 Eddie HungMerge branch 'map_cells_before_map_luts' into xc7srl
2019-04-04 Eddie Hungsynth_xilinx to map_cells before map_luts
2019-04-04 Eddie HungCleanup comments
2019-04-04 Eddie Hungt:$dff* -> t:$dff t:$dffe
2019-04-03 Eddie HungRemove handling for $pmux, since #895
2019-04-03 Eddie Hung-nosrl meant when -nobram
2019-04-03 Eddie HungRemove duplicate STARTUPE2
2019-04-03 Eddie HungDisable shregmap in synth_xilinx if -retime
2019-04-03 Eddie HungAdd changelog entry
2019-04-03 Eddie HungMerge pull request #913 from smunaut/fix_proc_mux
2019-04-03 Sylvain Munautproc_mux: Fix crash when trying to optimize non-existan...
2019-04-03 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-03 Clifford WolfMerge pull request #912 from YosysHQ/bram_addr_en
2019-04-03 Clifford WolfMerge pull request #910 from ucb-bar/memupdates
2019-04-02 David Shahmemory_bram: Consider read enable for address expansion...
2019-04-02 Eddie HungMerge pull request #895 from YosysHQ/pmux2shiftx
2019-04-01 Jim LawsonRefine memory support to deal with general Verilog...
2019-03-29 Clifford WolfMerge pull request #907 from YosysHQ/clifford/fix906
2019-03-29 Clifford WolfBuild Verilog parser with -DYYMAXDEPTH=100000, fixes...
2019-03-28 Clifford WolfMerge pull request #901 from trcwm/libertyfixes
2019-03-28 Clifford WolfMerge pull request #903 from YosysHQ/bram_reset_transp
2019-03-27 David Shahmemory_bram: Reset make_transp when growing read ports
2019-03-27 Niels MoseleyLiberty file parser now accepts superfluous ;
2019-03-27 Niels MoseleyLiberty file parser now accepts superfluous ;
2019-03-27 Niels MoseleyLiberty file parser now accepts superfluous ;
2019-03-27 Clifford WolfAdd "read -verific" and "read -noverific"
2019-03-27 Clifford WolfAdd "rename -output"
2019-03-27 Clifford WolfImprove "rename" help message
2019-03-26 Clifford WolfAdd "cutpoint -undef"
2019-03-26 Clifford WolfAdd "hdlname" attribute
2019-03-26 Clifford WolfFix "verific -extnets" for more complex situations
2019-03-25 Eddie Hungsynth_xilinx to use shregmap with -minlen 3
2019-03-25 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
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