gram.git
2020-06-11 Jean THOMASMake memory test code more verbose
2020-06-11 Jean THOMASFix write signal name for CSR (fixes #5)
2020-06-11 Jean THOMASRemove old commented code
2020-06-11 Jean THOMASRestrict exposed classes
2020-06-11 Jean THOMASAdd default case for _DownConverter Switch
2020-06-11 Jean THOMASMake non gram_* symbols local symbols (fixes #2)
2020-06-10 Jean THOMASRemove SDR/DDR/DDR2 modules (unsupported)
2020-06-10 Jean THOMASRemove get_csrs() (useless)
2020-06-10 Jean THOMASAdd test firmware
2020-06-10 Jean THOMASAdd link to LambdaConcept website
2020-06-10 Jean THOMASRemove unused files
2020-06-10 Jean THOMASAutopep8
2020-06-10 Jean THOMASRemove unnecessary import in DFII
2020-06-10 Jean THOMASAdd self._bridge to m.submodules (fixing #4)
2020-06-10 Jean THOMASRemove Peripheral inheritance in multiplexer
2020-06-10 Jean THOMASFix missing submodule statement in ECPIX5 example
2020-06-10 Jean THOMASUse sync as clock domain for crossbar
2020-06-10 Jean THOMASFix typos
2020-06-10 Jean THOMASFinish porting stream classes to nMigen
2020-06-09 Jean THOMASAdd stream Pipeline, fix bugs in gram.stream
2020-06-09 Jean THOMASAdd StrideConverter implementation
2020-06-09 Jean THOMASNew wishbone frontend
2020-06-09 Jean THOMASFix nMigen migration issue (DomainRenamer)
2020-06-09 Jean THOMASFix nMigen migration bug, and rename from LiteDRAM...
2020-06-09 Jean THOMASUpdate README according to the current API
2020-06-09 Jean THOMASAdd EOL
2020-06-09 Jean THOMASRefine libgram architecture
2020-06-09 Jean THOMASAdd gitignore for libgram
2020-06-09 Jean THOMASUpdate Makefile for library generation
2020-06-09 Jean THOMASAutopep8 on example code
2020-06-09 Jean THOMASAdd formatting script
2020-06-09 Jean THOMASRun autopep8
2020-06-09 Jean THOMASRework LiteDRAM wishbone frontend (wip)
2020-06-09 Jean THOMASExpose RAM size in gramCore
2020-06-08 Jean THOMASFix links in README
2020-06-08 Jean THOMASRework RAM port for nMigen compliance
2020-06-08 Jean THOMASRename LiteDRAM to gram
2020-06-08 Jean THOMASConnect dramcore to SoC bus in ECPIX-5 example
2020-06-08 Jean THOMASRename LiteDRAM to gram
2020-06-08 Jean THOMASUse CSRPrefixProxy for exposing CSR
2020-06-08 Jean THOMASAdd CSRPrefixProxy to gram.compat
2020-06-08 Jean THOMASUpdate documentation
2020-06-08 Jean THOMASAdd early code for libgram
2020-06-08 Jean THOMASFix bugs in ECP5DDRPHY instanciation
2020-06-08 Jean THOMASCleaning repo
2020-06-08 Jean THOMASMigrate FIFO frontend from Migen to nMigen
2020-06-08 Jean THOMASRework DFI interface code
2020-06-08 Jean THOMASClean unused code
2020-06-08 Jean THOMASAdd copyright
2020-06-08 Jean THOMASRemove setaddr for submodule instanciation
2020-06-08 Jean THOMASFix multiple drive issue
2020-06-08 Jean THOMASAdd copyright
2020-06-08 Jean THOMASFix PLL
2020-06-05 Jean THOMASRemove bandwidth meter
2020-06-05 Jean THOMASFix direction in stream assignment
2020-06-05 Jean THOMASFix typo
2020-06-05 Jean THOMASRemove useless variable
2020-06-05 Jean THOMASFix signal drive error
2020-06-05 Jean THOMASFix multi-driven signals in refresher
2020-06-04 Jean THOMASBugfixing
2020-06-04 Jean THOMASCorrect nMigen transition bugs
2020-06-04 Jean THOMASAdd dram core as submodule
2020-06-04 Jean THOMASMore nMigen conversion and fixes
2020-06-04 Jean THOMASAdd second clock
2020-06-04 Jean THOMASRemove diff pairs in ECPIX5Platform
2020-06-03 Jean THOMASInitial commit