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yosys.git
2016-08-18
Clifford Wolf
Bugfix in test_autotb
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2016-08-18
Clifford Wolf
Improved smtbmc vcd generation performance
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2016-08-17
Clifford Wolf
Added printing of code loc of failed asserts to yosys...
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2016-08-16
Clifford Wolf
Fixed default build config
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2016-08-16
Clifford Wolf
Merge pull request #203 from cr1901/master
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2016-08-16
William D....
Add MSYS2-compatible build.
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2016-08-16
Clifford Wolf
Use _Exit(0) on win32, always use _Exit(1) in log_error()
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2016-08-16
Clifford Wolf
Updated ABC to hg rev a86455b00da5
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2016-08-16
Clifford Wolf
Fixed use-after-free dict<> usage pattern in hierarchy.cc
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2016-08-15
Clifford Wolf
Updated ABC to hg rev 760ba358e790
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2016-08-15
Clifford Wolf
ABC mxe cross-build fix
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2016-08-15
Clifford Wolf
Minor fixes in show command
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2016-08-15
Clifford Wolf
Added greenpak4_dffinv
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2016-08-15
Clifford Wolf
Fixed upto handling in verilog back-end
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2016-08-14
Clifford Wolf
Merge pull request #200 from azonenberg/master
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2016-08-14
Andrew Zonenberg
greenpak4: Changed name of inverted output ports for...
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2016-08-14
Andrew Zonenberg
greenpak4: Added GP_DFFxI cells
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2016-08-14
Andrew Zonenberg
greenpak4: Renamed ports for better consistency (see...
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2016-08-11
Clifford Wolf
Merge pull request #198 from whitequark/master
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2016-08-10
whitequark
synth_greenpak4: use attrmvcp to move LOC from wires...
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2016-08-10
Clifford Wolf
Only allow posedge/negedge with 1 bit wide signals
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2016-08-10
Clifford Wolf
Fixed some compiler warnings in attrmap command
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2016-08-09
Clifford Wolf
Added "attrmap" command
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2016-08-09
Clifford Wolf
Added log_const() API
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2016-08-09
Clifford Wolf
Added "attrmvcp" pass
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2016-08-08
Yury Gribov
Use /proc/self/exe on Cygwin as well.
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2016-08-08
Clifford Wolf
Undo "preserve wire attributes in iopadmap" change...
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2016-08-06
Clifford Wolf
Added "test_autotb -seed" (and "autotest.sh -S")
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2016-08-06
Clifford Wolf
preserve wire attributes in iopadmap
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2016-08-06
Clifford Wolf
Fixed bug in parsing real constants
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2016-08-02
Clifford Wolf
Added "insbuf" command
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2016-07-30
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-07-30
Clifford Wolf
Added "write_verilog -defparam"
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2016-07-30
Clifford Wolf
Added "write_verilog -nodec -nostr"
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2016-07-27
Clifford Wolf
Added $initstate support to smtbmc flow
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2016-07-27
Clifford Wolf
Added SatGen support for $anyconst
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2016-07-27
Clifford Wolf
Removed $predict support from SatGen
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2016-07-27
Clifford Wolf
Added $anyconst and $aconst
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2016-07-27
Clifford Wolf
Added "read_verilog -dump_rtlil"
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2016-07-25
Clifford Wolf
Renamed AbstractCellEdgesDatabase::add_cell() to add_ed...
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2016-07-25
Clifford Wolf
Fixed a verilog parser memory leak
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2016-07-25
Clifford Wolf
Fixed parsing of empty positional cell ports
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2016-07-24
Clifford Wolf
Improvements in CellEdgesDatabase
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2016-07-24
Clifford Wolf
Added CellEdgesDatabase API
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2016-07-24
Clifford Wolf
Moved SatHelper::setup_init() code to SatHelper::setup()
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2016-07-23
Clifford Wolf
Added $initstate support to "sat" command
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2016-07-23
Clifford Wolf
No tristate warning message for "read_verilog -lib"
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2016-07-22
Clifford Wolf
Added satgen initstate support
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2016-07-21
Clifford Wolf
Using $initstate in "initial assume" and "initial assert"
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2016-07-21
Clifford Wolf
Added $initstate cell type and vlog function
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2016-07-21
Clifford Wolf
After reading the SV spec, using non-standard predict...
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2016-07-13
Clifford Wolf
Added basic support for $expect cells
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2016-07-13
Clifford Wolf
Added examples/smtbmc
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2016-07-13
Clifford Wolf
Merge pull request #191 from whitequark/json-module...
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2016-07-13
Clifford Wolf
Merge pull request #193 from azonenberg/master
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2016-07-12
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-07-12
Clifford Wolf
Minor bugfix in FSM reset state detection
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2016-07-12
whitequark
write_json: also write module attributes.
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2016-07-12
Andrew Zonenberg
Added GP_DAC cell
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2016-07-12
Andrew Zonenberg
Removed VOUT port of GP_BANDGAP
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2016-07-12
Andrew Zonenberg
Removed splitnets in prep for new gp4par parser
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2016-07-11
Clifford Wolf
Yosys-smtbmc: Support for hierarchical VCD dumping
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2016-07-11
Clifford Wolf
Moved smt2 yosys info parsing from smtbmc.py to smtio.py
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2016-07-11
Clifford Wolf
Added "prep -auto-top" and "synth -auto-top"
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2016-07-10
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-07-10
Clifford Wolf
Merge pull request #189 from whitequark/master
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2016-07-10
Clifford Wolf
Support for hierarchical designs in smt2 back-end
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2016-07-10
whitequark
greenpak4: add GP_COUNT{8,14}_ADV cells.
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2016-07-09
Clifford Wolf
Further improved fsm_detect output, attempt to detect...
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2016-07-09
Clifford Wolf
Added printing of some warning messages to fsm_detect
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2016-07-08
Clifford Wolf
Added warning about adding fsm_encoding attributes...
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2016-07-08
Clifford Wolf
Minor fixes in ice40_ff* passes for sloppy SB_DFF insta...
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2016-07-08
Clifford Wolf
Fixed mem assignment in left-hand-side concatenation
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2016-07-08
Clifford Wolf
Merge branch 'eddiehung-vtr'
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2016-07-08
Clifford Wolf
Restored blif "-true - .." behavior, use "-true + ...
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2016-07-08
Clifford Wolf
In BLIF, a .names without entries already always outputs 0
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2016-07-08
Clifford Wolf
Undo eddiehung-vtr Makefile changes
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-07-02
Clifford Wolf
Fixed autotest.sh handling of `timescale
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2016-07-01
Clifford Wolf
Merge branch 'assert-limit'
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2016-07-01
Clifford Wolf
Replaced "select -assert-limit" with -assert-max and...
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2016-07-01
eshellko
Added 'assert-limit' option for 'select' command
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2016-06-30
Clifford Wolf
Improved ice40_ffinit error reporting
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2016-06-21
Clifford Wolf
Merge pull request #181 from rubund/input_logic_allowed
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2016-06-20
Ruben Undheim
Allow defining input ports as "input logic" in SystemVe...
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2016-06-19
Clifford Wolf
Bugfix in "abc -script" handling
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2016-06-19
Clifford Wolf
Merge branch 'sv_packages' of https://github.com/rubund...
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2016-06-19
Clifford Wolf
Added "deminout"
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2016-06-18
Ruben Undheim
A few modifications after pull request comments
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2016-06-18
Clifford Wolf
Added "read_blif -sop"
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2016-06-18
Clifford Wolf
Added $sop support to BLIF back-end
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2016-06-18
Ruben Undheim
Added support for SystemVerilog packages with localpara...
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2016-06-17
Clifford Wolf
Added "dc2" to default ABC scripts
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2016-06-17
Clifford Wolf
Fixed init issue in mem2reg_test2 test case
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2016-06-17
Clifford Wolf
Added "abc -I <num> -P <num>"
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2016-06-17
Clifford Wolf
Added $sop SAT model
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2016-06-17
Clifford Wolf
Improved support for $sop cells
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2016-06-17
Clifford Wolf
Added $sop cell type and "abc -sop"
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2016-06-17
Clifford Wolf
Updated ABC to hg rev b5df6e2b76f0
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2016-06-09
Clifford Wolf
Added "nlutmap -assert"
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