riscv-isa-sim.git
2018-10-14 Luke Kenneth... redirect subtract through rv_sub
2018-10-14 Luke Kenneth... redirect add to rv_add
2018-10-14 Luke Kenneth... redirect add to rv_add
2018-10-14 Luke Kenneth... bit of a mess: attempted to create a complete arithmeti...
2018-10-13 Luke Kenneth... rename _zext_xlen
2018-10-13 Luke Kenneth... add sv_reg_t
2018-10-12 Luke Kenneth... redirect WRITE_FRD including different types (128/64/32)
2018-10-12 Luke Kenneth... add WRITE_FRD macro redirect
2018-10-12 Luke Kenneth... changed style, can revert changes to amomin/max
2018-10-12 Luke Kenneth... add frs2 redirect
2018-10-12 Luke Kenneth... add RS3 replacement
2018-10-12 Luke Kenneth... simplify sv_proc_t redirection of RS1-3 / FRS1 macrhos
2018-10-12 Luke Kenneth... redirect RS2 to sv_proc_t class
2018-10-12 Luke Kenneth... proof-of-concept, redirect RS1 to class sv_proc_t
2018-10-12 Luke Kenneth... combination of redirection through a "property" class...
2018-10-11 Luke Kenneth... redirect instructions through a class called sv_proc_t
2018-10-11 Luke Kenneth... more explicit testing, duplicating header file algorith...
2018-10-11 Luke Kenneth... whoops run from 0-255 not 0-254, and other test corrections
2018-10-11 Luke Kenneth... add some operator tests for int8_t being typecast to...
2018-10-11 Luke Kenneth... add more experimenting on operators
2018-10-10 Luke Kenneth... add operators test class
2018-10-10 Luke Kenneth... add operators library to contain operator-overloads...
2018-10-09 Luke Kenneth... get predicated-vectorised branch working
2018-10-09 Luke Kenneth... save branch address and predication merged result,...
2018-10-09 Luke Kenneth... add explanatory comment
2018-10-09 Luke Kenneth... add explanatory comment
2018-10-09 Luke Kenneth... start adding explicit twin-predicated branch identifica...
2018-10-09 Luke Kenneth... extend sv register file from 64 to 128 after discussion.
2018-10-07 Luke Kenneth... override setpc macro so that sv can redirect it in...
2018-10-07 Luke Kenneth... swap #ifdef USING_NOREGS so that it is possible to...
2018-10-07 Luke Kenneth... add rd bit-setting function
2018-10-07 Luke Kenneth... add extra debug printing for c.lwsp
2018-10-07 Luke Kenneth... add rvc_swsp_imm sv overload, provides vector unit...
2018-10-06 Luke Kenneth... c.swsp and c.fswsp predication and offset enabling
2018-10-06 Luke Kenneth... allow x2 (sp) to be redirected in C.LWSP
2018-10-06 Luke Kenneth... temporary hack disabling SV in anything other than...
2018-10-06 Luke Kenneth... whoops inverted ldsp and lwsp immediates
2018-10-06 Luke Kenneth... create ldsp immediate offset overrides
2018-10-06 Luke Kenneth... add in predication for immediate, for C.LWSP
2018-10-05 Luke Kenneth... reorganise src and dest vector-element offsets
2018-10-05 Luke Kenneth... add srcoffs and destoffs sv state, alter CSRs
2018-10-04 Luke Kenneth... reorganise twin-predication
2018-10-04 Luke Kenneth... big reorganisation to support twin-predication
2018-10-03 Luke Kenneth... add in twin-predication identification
2018-10-03 Luke Kenneth... decided not to change the behaviour of LOAD/STORE
2018-10-02 Luke Kenneth... start work on parallelsing LOAD, pass in parameter...
2018-10-02 Luke Kenneth... debug print for floating-point regs
2018-10-01 Luke Kenneth... add comment explaining why invert isnt done in zeroing...
2018-10-01 Luke Kenneth... add comment explaining use of insn._rd() in zeroing
2018-10-01 Luke Kenneth... whoops vloop continuation logic the wrong way round
2018-10-01 Luke Kenneth... skip parallelisation of complex LR/SC operations
2018-10-01 Luke Kenneth... identify type of instruction with additional #defines
2018-09-30 Luke Kenneth... add a #define to id_regs.py which indicates name of...
2018-09-30 Luke Kenneth... list of instructions to avoid parallelising
2018-09-30 Luke Kenneth... update template comment
2018-09-30 Luke Kenneth... lots of debugging of predication, found other errors
2018-09-30 Luke Kenneth... add sv support for zeroing predication in dest register
2018-09-30 Luke Kenneth... add in predication to sv instruction execution
2018-09-30 Luke Kenneth... start linking in predication into sv
2018-09-30 Luke Kenneth... use an alternative logic for detecting scalar / loop-end
2018-09-30 Luke Kenneth... add compressed-identifying patterns to id_regs.py
2018-09-30 Luke Kenneth... fix code template for when SPIKE_SIMPLEV is not defined
2018-09-30 Luke Kenneth... yuk. break id_regs.py being a generic tool by skipping...
2018-09-29 Luke Kenneth... fix bug in sv template where FRS2 was checking rs3
2018-09-29 Luke Kenneth... add checks for RVC registers to sv template
2018-09-29 Luke Kenneth... add sv_insn_t overloads for rvc registers
2018-09-29 Luke Kenneth... also arrange for id_regs.py to identify compressed...
2018-09-29 Luke Kenneth... a LOT of debugging and fixing, sv loop actually working
2018-09-29 Luke Kenneth... move SV CSRs to user-read-write
2018-09-29 Luke Kenneth... add near-duplicate of SV CFG REG CSRs, for predication
2018-09-29 Luke Kenneth... add implementation of CSR SV CFG regs 0-7
2018-09-29 Luke Kenneth... assign SV REG CSRs (using new union ability)
2018-09-29 Luke Kenneth... make sv csr tables a union so they can be assigned...
2018-09-29 Luke Kenneth... add support for CSR_SVVL to CSRRWI as well
2018-09-29 Luke Kenneth... fix bug in CSR set SVVL: val has already been looked up
2018-09-29 Luke Kenneth... add stub for SV REG configs
2018-09-29 Luke Kenneth... stop a compiler warning
2018-09-29 Luke Kenneth... reorganise from moving sv_pred_* and sv_reg_* tables...
2018-09-29 Luke Kenneth... have to move SV CSRs into processor_t
2018-09-29 Luke Kenneth... add 8 CSRs for registers and predication each
2018-09-29 Luke Kenneth... whoops dont need separate SVSETVL/SVGETVL CSRs
2018-09-29 Luke Kenneth... revert addition of svsetvl as an actual opcode, add...
2018-09-29 Luke Kenneth... Revert "sv setvl as a csr not going to work, add getvl...
2018-09-29 Luke Kenneth... Revert "manually add svsetvl instruction"
2018-09-28 Luke Kenneth... manually add svsetvl instruction
2018-09-28 Luke Kenneth... sv setvl as a csr not going to work, add getvl only
2018-09-27 Luke Kenneth... adding sv vector length CSR to processor state, and...
2018-09-27 Luke Kenneth... add sv predication function
2018-09-26 Luke Kenneth... save some cpu cycles by |ing the checks for vectorop...
2018-09-26 Luke Kenneth... whoops vectorop has to be |= not &= to accumulate ...
2018-09-26 Luke Kenneth... cache the sv redirected register values on each loop
2018-09-26 Luke Kenneth... remembered that the use of sv registers have to be...
2018-09-26 Luke Kenneth... clarify comments on (key strategic) sv_insn_t::remap...
2018-09-26 Luke Kenneth... actually implement sv register re-mapping
2018-09-26 Luke Kenneth... ok this is tricky: an extra parameter has to be passed...
2018-09-26 Luke Kenneth... move sv remap function to sv.cc (not inline)
2018-09-26 Luke Kenneth... check if register redirection is active, and if vectori...
2018-09-26 Luke Kenneth... comment why sv_insn_t is set up the way it is; add...
2018-09-26 Luke Kenneth... easier to #define USING_NOREGS if the opcode does not...
2018-09-26 Luke Kenneth... include auto-generated identification of use of registe...
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