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yosys.git
2019-01-07
Clifford Wolf
Switch "bugpoint" from system() to run_command()
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2019-01-07
Clifford Wolf
Merge pull request #783 from whitequark/bugpoint
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2019-01-07
whitequark
bugpoint: new pass.
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2019-01-06
Clifford Wolf
Merge pull request #780 from phire/rename_from_wire
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2019-01-06
Scott Mansell
Rename cells based on the wires they drive.
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2019-01-05
Clifford Wolf
Add skeleton Yosys-Libero igloo2 example project
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2019-01-05
Clifford Wolf
Bugfix in Verilog string handling
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2019-01-04
Clifford Wolf
Merge pull request #777 from mmicko/achronix_cell_sim_fix
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2019-01-04
Miodrag Milanovic
Fix cells_sim.v for Achronix FPGA
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2019-01-04
Clifford Wolf
Remove -m32 Verific eval lib build instructions
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2019-01-04
Clifford Wolf
Merge pull request #776 from mmicko/unify_noflatten
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2019-01-04
Clifford Wolf
Update Verific default path
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2019-01-04
Miodrag Milanovic
Unify usage of noflatten among architectures
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2019-01-03
Clifford Wolf
Merge pull request #775 from whitequark/opt_flowmap
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2019-01-03
whitequark
flowmap: new techmap pass.
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2019-01-02
Clifford Wolf
Merge pull request #770 from whitequark/opt_expr_cmp
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2019-01-02
whitequark
opt_expr: improve simplification of comparisons with...
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2019-01-02
Clifford Wolf
Merge pull request #755 from Icenowy/anlogic-dram-init
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2019-01-02
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-01-02
Clifford Wolf
Merge pull request #750 from Icenowy/anlogic-ff-init
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2019-01-02
Clifford Wolf
Merge pull request #773 from whitequark/opt_lut_elim_fixes
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2019-01-02
Clifford Wolf
Merge pull request #772 from whitequark/synth_lut
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2019-01-02
Clifford Wolf
Merge pull request #771 from whitequark/techmap_cmp2lut
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2019-01-02
Clifford Wolf
Improve VerificImporter support for writes to asymmetri...
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2019-01-02
Clifford Wolf
Fix VerificImporter asymmetric memories error message
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2019-01-02
Clifford Wolf
Merge pull request #769 from whitequark/typos
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2019-01-02
whitequark
Fix typographical and grammatical errors and inconsiste...
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2019-01-02
whitequark
opt_lut: reflect changes in sigmap.
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2019-01-02
whitequark
opt_lut: use a worklist, and revisit cells affected...
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2019-01-02
whitequark
opt_lut: count eliminated cells, and set opt.did_someth...
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2019-01-02
whitequark
synth_ice40: use 4-LUT coarse synthesis mode.
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2019-01-02
whitequark
synth: add k-LUT mode.
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2019-01-02
whitequark
synth: improve script documentation. NFC.
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2019-01-02
whitequark
cmp2lut: new techmap pass.
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2019-01-02
whitequark
opt_expr: refactor simplification of unsigned X<onehot...
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2019-01-02
whitequark
opt_expr: refactor simplification of signed X>=0 and...
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2019-01-02
whitequark
opt_expr: simplify any unsigned comparisons with all...
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2019-01-01
Clifford Wolf
Merge pull request #768 from whitequark/opt_lut_elim
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2018-12-31
whitequark
opt_lut: eliminate LUTs evaluating to constants or...
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2018-12-31
Clifford Wolf
Fix handling of (* keep *) wires in wreduce
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2018-12-31
Clifford Wolf
Merge pull request #766 from Icenowy/anlogic-latches
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2018-12-29
Larry Doolittle
Fix 7 instances of add_share_file to add_gen_share_file
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2018-12-29
Larry Doolittle
Squelch a little more trailing whitespace
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2018-12-25
Icenowy Zheng
anlogic: add latch cells
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2018-12-23
Clifford Wolf
Merge pull request #761 from whitequark/proc_clean_partial
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2018-12-23
Clifford Wolf
Add "read_ilang -[no]overwrite"
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2018-12-23
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys
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2018-12-23
whitequark
proc_clean: remove any empty cases if all cases use...
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2018-12-22
Clifford Wolf
Merge pull request #757 from whitequark/manual_mem
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2018-12-22
whitequark
proc_clean: remove any empty cases at the end of the...
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2018-12-21
whitequark
manual: make description of $meminit ports match reality.
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2018-12-21
Clifford Wolf
Merge pull request #758 from whitequark/tcl_script_args
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2018-12-21
Clifford Wolf
Merge pull request #759 from whitequark/memory_collect_...
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2018-12-21
whitequark
memory_collect: do not truncate 'x from \INIT.
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2018-12-20
whitequark
manual: fix typos.
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2018-12-20
whitequark
tcl: add support for passing arguments to scripts.
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2018-12-20
whitequark
manual: document $meminit cell and memory_* passes.
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2018-12-19
Icenowy Zheng
anlogic: implement DRAM initialization
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2018-12-19
Clifford Wolf
Merge pull request #752 from Icenowy/anlogic-lut-cost
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2018-12-19
Clifford Wolf
Merge pull request #753 from Icenowy/anlogic-makefile-fix
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2018-12-19
Clifford Wolf
Merge pull request #749 from Icenowy/anlogic-dram-fix
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2018-12-19
Icenowy Zheng
anlogic: fix Makefile.inc
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2018-12-19
Icenowy Zheng
Anlogic: let LUT5/6 have more cost than LUT4-
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2018-12-18
Clifford Wolf
Minor style fixes
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2018-12-18
Clifford Wolf
Merge pull request #748 from makaimann/add-btor-ops
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2018-12-18
Clifford Wolf
Merge pull request #751 from daveshah1/fix_589
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2018-12-18
David Shah
memory_dff: Fix typo when checking init value
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2018-12-18
Clifford Wolf
Fix segfault in AST simplify
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2018-12-18
Icenowy Zheng
anlogic: set the init value of DFFs
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2018-12-18
Icenowy Zheng
Add "dffinit -noreinit" parameter
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2018-12-18
Clifford Wolf
Improve src tagging (using names and attrs) of cells...
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2018-12-18
Icenowy Zheng
Add "dffinit -strinit high low"
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2018-12-18
Icenowy Zheng
anlogic: fix dbits of Anlogic Eagle DRAM16X4
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2018-12-17
makaimann
Add btor ops for $mul, $div, $mod and $concat
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2018-12-17
Clifford Wolf
Merge pull request #746 from Icenowy/anlogic-dram
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2018-12-17
Clifford Wolf
Merge pull request #742 from whitequark/changelog
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2018-12-17
Clifford Wolf
Merge pull request #741 from whitequark/ilang_slice_sigspec
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2018-12-17
Clifford Wolf
Merge pull request #744 from whitequark/write_verilog_...
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2018-12-17
Icenowy Zheng
anlogic: add support for Eagle Distributed RAM
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2018-12-17
Icenowy Zheng
Revert "Leave only real black box cells"
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2018-12-16
Clifford Wolf
Merge pull request #745 from YosysHQ/revert-714-abc_pre...
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2018-12-16
Clifford Wolf
Revert "Proof-of-concept: preserve naming through ABC...
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2018-12-16
whitequark
write_verilog: handle the $shift cell.
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2018-12-16
whitequark
Update CHANGELOG.
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2018-12-16
whitequark
read_ilang: allow slicing sigspecs.
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2018-12-16
Clifford Wolf
Merge pull request #736 from whitequark/select_assert_list
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2018-12-16
whitequark
select: print selection if a -assert-* flag causes...
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2018-12-16
Clifford Wolf
Rename "fine:" label to "map:" in "synth_ice40"
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2018-12-16
Clifford Wolf
Merge pull request #704 from webhat/feature/fix-awk
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2018-12-16
whitequark
write_verilog: add a missing newline.
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2018-12-16
Clifford Wolf
Merge pull request #738 from smunaut/issue_737
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2018-12-16
Clifford Wolf
Merge pull request #735 from daveshah1/trifixes
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2018-12-16
Clifford Wolf
Merge pull request #739 from whitequark/patch-1
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2018-12-16
whitequark
Add .editorconfig file.
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2018-12-16
Clifford Wolf
Fix equiv_opt indenting
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2018-12-16
Clifford Wolf
Merge pull request #724 from whitequark/equiv_opt
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2018-12-16
Clifford Wolf
Merge pull request #734 from grahamedgecombe/fix-shuffl...
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2018-12-16
Clifford Wolf
Merge pull request #730 from smunaut/ffssr_dont_touch
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2018-12-16
Clifford Wolf
Merge pull request #729 from whitequark/write_verilog_i...
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2018-12-16
Clifford Wolf
Merge pull request #725 from olofk/ram4k-init
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