2023-06-02 |
Luke Kenneth... | add stub reset_xflags function |
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2023-06-02 |
Dmitry Selyutin | minor_19.csv: convert RA to RA0 for minmax |
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2023-06-02 |
Luke Kenneth... | add FPSCR to Test API (ExpectedState, SimState). untested |
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2023-06-02 |
Luke Kenneth... | add FPSCR to ISACaller |
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2023-06-02 |
Luke Kenneth... | notes: make FPSCR definition more like MSR (see openpow... |
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2023-06-02 |
Luke Kenneth... | drastically simplify fpscr.py. extreme overcomplexity... |
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2023-06-02 |
Luke Kenneth... | add comment about why the new check has been added |
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2023-06-02 |
Luke Kenneth... | get table down to under 80 chars per line |
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2023-06-02 |
Jacob Lifshay | fix fpscr table parser error reporting |
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2023-06-02 |
Jacob Lifshay | add FPSCRState and FPSCRRecord and a FPSCR smoke-test |
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2023-06-02 |
Jacob Lifshay | add initial fmv/fcvt tests, though they're broken due... |
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2023-06-02 |
Jacob Lifshay | add check that generated .py files are in .gitignore |
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2023-06-02 |
Jacob Lifshay | verify fields.txt forms' field separators ('|') line... |
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2023-06-02 |
Konstantinos... | merge maddrs/msubrs, unit tests changed accordingly |
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2023-06-02 |
Konstantinos... | Add 2 more instructions to help with 2-coeff butterfly |
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2023-06-02 |
Konstantinos... | use a simpler way to do the same thing |
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2023-06-02 |
Konstantinos... | Handle large 64-bit values, but only the low 64-bit... |
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2023-06-02 |
Konstantinos... | do proper rounding, no rounding for SH=0 (for now)... |
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2023-06-02 |
Konstantinos... | Result needs rounding so add +1 to prod* |
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2023-06-02 |
Konstantinos... | handle negatives correctly by adding sign bit to final... |
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2023-06-02 |
Konstantinos... | almost there, positive values work, negative values... |
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2023-06-02 |
Konstantinos... | use proper register sizes |
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2023-06-02 |
Konstantinos... | MULS instead of MUL, RA instead of RT in in1 |
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2023-06-02 |
Konstantinos... | Turns out DCTI-Form is another variant of A-Form |
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2023-06-02 |
Konstantinos... | minor fixes in pseudocode, CONST_UI->CONST_SH in minor_... |
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2023-06-02 |
Konstantinos... | WIP: maddsubrs initial approach |
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2023-06-02 |
Luke Kenneth... | maddsubrs no longer has CR0 |
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2023-06-02 |
Jacob Lifshay | fix forgotten stuff from last commit |
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2023-06-02 |
Jacob Lifshay | add fcvt/fmv -- no tests yet |
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2023-06-02 |
Jacob Lifshay | support calling functions with no args in pseudocode |
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2023-06-02 |
Jacob Lifshay | show actual mdwn source location in backtrace when... |
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2023-06-02 |
Jacob Lifshay | move Assign to parser class in prep for improving synta... |
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2023-06-02 |
Jacob Lifshay | add all fmv*/fcvt* fields |
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2023-06-02 |
Jacob Lifshay | split XO-Form's RA field in prep for adding fcvttg... |
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2023-06-02 |
Jacob Lifshay | remove testing with INSNDB=true since that now does... |
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2023-06-02 |
Jacob Lifshay | comment fmin*/fmax* since they're being replaced with... |
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2023-06-02 |
Jacob Lifshay | fix non-zero assembly operands being zero |
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2023-06-02 |
Jacob Lifshay | update SV csvs |
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2023-06-02 |
Luke Kenneth... | add links between decode and issue |
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2023-06-02 |
Luke Kenneth... | reserve writes in Issue Phase, add comment |
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2023-06-02 |
Luke Kenneth... | add Issue phase and writes/reads possible in CPU |
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2023-06-02 |
Luke Kenneth... | add Decode and CPU classes |
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2023-06-02 |
Luke Kenneth... | add quick preamble header |
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2023-06-02 |
Luke Kenneth... | update comments and correct retiring, remove registers... |
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2023-06-02 |
Luke Kenneth... | start on cycle-accurate model of inorder core |
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2023-06-02 |
Luke Kenneth... | ffnmadds converted to 3-operand |
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2023-06-02 |
Luke Kenneth... | converted ffnmadds to 3-operand |
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2023-06-02 |
Luke Kenneth... | ffmsubs number of operands reduced to match ffmadds |
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2023-06-02 |
Dmitry Selyutin | power_insn: forbid zero for non-zero operands |
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2023-06-02 |
Dmitry Selyutin | power_insn: drop registers remapping hack |
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2023-06-02 |
Dmitry Selyutin | power_insn: support int and index opcode methods |
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2023-06-02 |
Luke Kenneth... | reduce number of operands to ffmadds as well |
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2023-06-02 |
Jacob Lifshay | prefix-sum remap works! |
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2023-06-02 |
Jacob Lifshay | change order to tuple in remap preduce tests/demos... |
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2023-06-02 |
Jacob Lifshay | fix <u and >u with int arguments |
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2023-06-02 |
Luke Kenneth... | reduce fdmadds down to only 3 operands, RT-overwrite... |
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2023-06-02 |
Luke Kenneth... | add SVSHAPE setup for parallel/prefix but it refuses... |
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2023-06-02 |
Luke Kenneth... | add implicit rs detection for maddsubrs |
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2023-06-02 |
Luke Kenneth... | link in new parallel-prefix REMAP schedule |
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2023-06-02 |
Jacob Lifshay | add scan/prefix-sum support to copy of parallel-reduce... |
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2023-06-02 |
Jacob Lifshay | format remap_preduce_yield.py |
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2023-06-02 |
Dmitry Selyutin | power_insn: deprecate ff/pr common code |
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2023-06-02 |
Dmitry Selyutin | power_insn: deprecate PR specifier |
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2023-06-02 |
Dmitry Selyutin | power_insn: deprecate normal PR mode |
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2023-06-02 |
Dmitry Selyutin | pysvp64dis: deprecate pr tests |
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2023-06-02 |
Dmitry Selyutin | pysvp64asm: deprecate pr tests |
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2023-06-02 |
Dmitry Selyutin | power_enums: sync forms |
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2023-06-02 |
Luke Kenneth... | add CW and CW2 Form |
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2023-06-02 |
Luke Kenneth... | check RC1, add data-dependent fail-first LD/ST test |
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2023-06-02 |
Jacob Lifshay | replace min/max[su][.] with minmax[.] |
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2023-06-02 |
Jacob Lifshay | add unofficial and comment2 columns to minor_19.csv |
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2023-06-02 |
Jacob Lifshay | add MM-form |
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2023-06-02 |
Jacob Lifshay | fix bug where pseudo-code assignments modify more than... |
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2023-06-02 |
Jacob Lifshay | rename/convert/merge XLCASTU/XLCASTS to EXTZXL/EXTSXL |
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2023-06-02 |
Jacob Lifshay | rewrite all uses of XLCASTU/XLCASTS |
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2023-06-02 |
Jacob Lifshay | add EXTZ since it's in PowerISA v3.1B (see lbz for... |
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2023-06-02 |
Jacob Lifshay | fix EXTSXL/XLCASTU/XLCASTS when inputs are python ints |
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2023-06-02 |
Jacob Lifshay | use proper cast function |
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2023-06-02 |
Jacob Lifshay | change XLEN-ification |
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2023-06-02 |
Jacob Lifshay | change extsb/h/w to scale based on XLEN rather than... |
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2023-06-02 |
Jacob Lifshay | add shaddw |
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2023-06-02 |
Jacob Lifshay | spelling fix |
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2023-06-02 |
Dmitry Selyutin | media: migrate to binutils |
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2023-06-02 |
Dmitry Selyutin | sv_binutils: fix broken script |
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2023-06-02 |
Luke Kenneth... | add power_decode_svp64_rm.py capability for new LD... |
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2023-06-02 |
Luke Kenneth... | add quick test_pysvp64dis.py of LD/ST data-dependent... |
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2023-06-02 |
Luke Kenneth... | https://bugs.libre-soc.org/show_bug.cgi?id=1047 |
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2023-06-02 |
Luke Kenneth... | whitespace cleanup (80 char per line hard limit) |
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2023-06-02 |
Luke Kenneth... | comment about massive unnecessary code-duplication... |
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2023-06-02 |
Luke Kenneth... | fix setvl unit test which happened to use deprecated |
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2023-06-02 |
Jacob Lifshay | fix add-like CA/OV outputs |
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2023-06-02 |
Jacob Lifshay | fix broken test case |
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2023-06-02 |
Jacob Lifshay | add addex to simulator |
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2023-06-02 |
Jacob Lifshay | fix typo when getting pseudo-code output variables |
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2023-06-02 |
Jacob Lifshay | switch to testing Rc=1 variants |
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2023-06-02 |
Jacob Lifshay | fix `neg[o].` causing the simulator to raise TypeError |
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2023-06-02 |
Jacob Lifshay | add case_nego_ |
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2023-06-02 |
Jacob Lifshay | rename le -> lt since CR bits are lt, gt, eq, and so... |
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2023-06-02 |
Luke Kenneth... | remove DCT/iDCT redundant modes which require less... |
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2023-06-02 |
Jacob Lifshay | add test cases for ca/ov outputs of a bunch of add... |
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