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yosys.git
2019-05-11
Clifford Wolf
Add "fmcombine -initeq -anyeq"
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2019-05-11
Clifford Wolf
Add "stat -tech xilinx"
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2019-05-09
Clifford Wolf
Merge pull request #1000 from bwidawsk/synth-format
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2019-05-09
Ben Widawsky
Fix formatting for synth_intel.cc
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2019-05-09
Ben Widawsky
Add a .clang-format
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2019-05-09
Clifford Wolf
Add $stop to documentation
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2019-05-08
Clifford Wolf
Remove added newline (by re-running minisat 00_UPDATE.sh)
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2019-05-08
Clifford Wolf
Merge pull request #991 from kristofferkoch/gcc9-warnings
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2019-05-08
Kristoffer...
Fix all warnings that occurred when compiling with...
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2019-05-08
Clifford Wolf
Merge pull request #998 from mdaiter/get_bool_attribute...
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2019-05-08
Matthew Daiter
Minor optimization to get_attribute_bool
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2019-05-07
Clifford Wolf
Add test case from #997
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2019-05-07
Clifford Wolf
Fix handling of partial init attributes in write_verilo...
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2019-05-07
Clifford Wolf
Merge pull request #996 from mdaiter/ceil_log2_opts
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2019-05-07
Matthew Daiter
Optimize ceil_log2 function
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2019-05-07
Clifford Wolf
Add "synth_xilinx -arch"
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2019-05-07
Clifford Wolf
More opt_clean cleanups
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2019-05-06
Clifford Wolf
Merge pull request #946 from YosysHQ/clifford/specify
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2019-05-06
Clifford Wolf
Merge pull request #975 from YosysHQ/clifford/fix968
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2019-05-06
Clifford Wolf
Merge pull request #871 from YosysHQ/verific_import
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2019-05-06
Clifford Wolf
Add tests/various/chparam.sh
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2019-05-06
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys into...
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2019-05-06
Clifford Wolf
Fix the other bison warning in ilang_parser.y
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2019-05-06
Clifford Wolf
Bugfix in peepopt_shiftmul.pmg
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2019-05-06
Clifford Wolf
Merge pull request #992 from bwidawsk/bison-fix
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2019-05-06
Clifford Wolf
Merge pull request #989 from YosysHQ/dave/abc_name_improve
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2019-05-06
Clifford Wolf
Fix bug in "expose -input"
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2019-05-06
Clifford Wolf
Cleanups in opt_clean
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2019-05-06
Clifford Wolf
Improve tests/various/specify.ys
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2019-05-06
Clifford Wolf
Add "real" keyword to ilang format
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2019-05-06
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys into...
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2019-05-06
Ben Widawsky
verilog_parser: Fix Bison warning
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2019-05-04
Clifford Wolf
Merge pull request #988 from YosysHQ/clifford/fix987
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2019-05-04
David Shah
abc: Fix handling of postfixed names (e.g. for retiming)
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2019-05-04
David Shah
abc: Improve name recovery
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2019-05-04
Clifford Wolf
Improve opt_clean handling of unused wires
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2019-05-04
Clifford Wolf
Add support for SVA "final" keyword
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2019-05-04
Clifford Wolf
Improve write_verilog specify support
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2019-05-04
Clifford Wolf
Update README
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2019-05-04
Clifford Wolf
Add approximate support for SV "var" keyword, fixes...
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2019-05-03
Eddie Hung
More testing
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2019-05-03
Eddie Hung
Fix spacing
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2019-05-03
Eddie Hung
Add quick-and-dirty specify tests
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2019-05-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into cliff...
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2019-05-03
Eddie Hung
Rename cells_map.v to prevent clash with ff_map.v
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2019-05-03
Eddie Hung
iverilog with simcells.v as well
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2019-05-03
Clifford Wolf
Add "hierarchy -chparam" support for non-verific top...
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2019-05-03
Eddie Hung
log_warning_noprefix -> log_warning as per review
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2019-05-03
Eddie Hung
For hier_tree::Elaborate() also include SV root modules...
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2019-05-03
Eddie Hung
Fix verific_parameters construction, use attribute...
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2019-05-03
Eddie Hung
WIP -chparam support for hierarchy when verific
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2019-05-03
Eddie Hung
verific_import() changes to avoid ElaborateAll()
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2019-05-03
Clifford Wolf
Merge pull request #969 from YosysHQ/clifford/pmgenstuff
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2019-05-03
Clifford Wolf
Merge pull request #984 from YosysHQ/eddie/fix_982
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2019-05-03
Eddie Hung
Revert "synth_xilinx to call dffinit with -noreinit"
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2019-05-03
Eddie Hung
If init is 1'bx, do not add to dict as per @cliffordwolf
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2019-05-03
Eddie Hung
Revert "dffinit -noreinit to silently continue when...
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2019-05-03
Clifford Wolf
Merge pull request #976 from YosysHQ/clifford/fix974
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2019-05-03
Clifford Wolf
Merge pull request #985 from YosysHQ/clifford/fix981
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2019-05-03
Clifford Wolf
Fix typo in tests/svinterfaces/runone.sh
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2019-05-03
Clifford Wolf
Merge pull request #979 from jakobwenzel/svinterfacesTe...
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2019-05-03
Clifford Wolf
Improve opt_expr and opt_clean handling of (partially...
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2019-05-03
Clifford Wolf
Further improve unused-detection for opt_clean driver...
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2019-05-03
Clifford Wolf
Improve unused-detection for opt_clean driver-driver...
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2019-05-03
Clifford Wolf
Update pmgen documentation
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2019-05-03
Clifford Wolf
Fix typo
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2019-05-03
Eddie Hung
synth_xilinx to call dffinit with -noreinit
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2019-05-03
Eddie Hung
dffinit -noreinit to silently continue when init value...
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2019-05-02
Jakob Wenzel
fail svinterfaces testcases on yosys error exit
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2019-05-02
Clifford Wolf
Merge pull request #963 from YosysHQ/eddie/synth_xilinx...
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2019-05-02
Eddie Hung
Merge pull request #978 from ucb-bar/fmtfirrtl
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2019-05-02
Eddie Hung
Back to passing all xc7srl tests!
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2019-05-02
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-05-01
Eddie Hung
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-05-01
Jim Lawson
Re-indent firrtl.cc:struct memory - no functional change.
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2019-05-01
Clifford Wolf
Merge branch 'clifford/fix883'
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2019-05-01
Clifford Wolf
Add missing enable_undef to "sat -tempinduct-def",...
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2019-05-01
Clifford Wolf
Merge pull request #977 from ucb-bar/fixfirrtlmem
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2019-05-01
Jim Lawson
Fix #938 - Crash occurs in case when use write_firrtl...
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2019-05-01
Clifford Wolf
Fix floating point exception in qwp, fixes #923
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2019-05-01
Clifford Wolf
Add splitcmplxassign test case and silence splitcmplxas...
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2019-05-01
Clifford Wolf
Fix width detection of memory access with bit slice...
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2019-05-01
Clifford Wolf
Add additional test cases for for-loops
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2019-05-01
Clifford Wolf
Silently resolve completely unused cell-vs-const driver...
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2019-05-01
Clifford Wolf
Re-enable "final loop assignment" feature
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2019-04-30
Clifford Wolf
Fix segfault in wreduce
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2019-04-30
Clifford Wolf
Disabled "final loop assignment" feature
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2019-04-30
Clifford Wolf
Merge pull request #972 from YosysHQ/clifford/fix968
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2019-04-30
Clifford Wolf
Merge pull request #966 from YosysHQ/clifford/fix956
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2019-04-30
Clifford Wolf
Merge pull request #962 from YosysHQ/eddie/refactor_syn...
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2019-04-30
Clifford Wolf
Merge branch 'master' into eddie/refactor_synth_xilinx
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2019-04-30
Clifford Wolf
Merge pull request #973 from christian-krieg/feature...
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2019-04-30
Clifford Wolf
Include filename in "Executing Verilog-2005 frontend...
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2019-04-30
Clifford Wolf
Fix performance bug in RTLIL::SigSpec::operator==(...
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2019-04-30
Clifford Wolf
Add final loop variable assignment when unrolling for...
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2019-04-30
Clifford Wolf
Add handling of init attributes in "opt_expr -undriven"
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2019-04-30
Benedikt Tutzer
Merge branch 'master' of https://github.com/YosysHQ...
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2019-04-30
Benedikt Tutzer
Cleaned up root directory
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2019-04-30
Clifford Wolf
Add peepopt_muldiv, fixes #930
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2019-04-30
Clifford Wolf
pmgen progress
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