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yosys.git
2018-11-01 Clifford WolfAdd support for signed $shift/$shiftx in smt2 back-end commit | commitdiff | tree
2018-10-31 Clifford WolfMerge branch 'igloo2' commit | commitdiff | tree
2018-10-31 Clifford WolfFix sf2 LUT interface commit | commitdiff | tree
2018-10-31 Clifford WolfBasic SmartFusion2 and IGLOO2 synthesis support commit | commitdiff | tree
2018-10-30 Clifford WolfMerge pull request #680 from jburgess777/fix-empty... commit | commitdiff | tree
2018-10-28 Jon BurgessAvoid assert when label is an empty string commit | commitdiff | tree
2018-10-25 Clifford WolfMerge pull request #678 from whentze/master commit | commitdiff | tree
2018-10-25 Clifford WolfFix minor typo in error message commit | commitdiff | tree
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error commit | commitdiff | tree
2018-10-24 Udi FinkelsteinRename the generic "Syntax error" message from the... commit | commitdiff | tree
2018-10-23 Clifford WolfMerge pull request #677 from daveshah1/ecp5_dsp commit | commitdiff | tree
2018-10-22 whentzefix unhandled std::out_of_range when calling yosys... commit | commitdiff | tree
2018-10-22 David Shahecp5: Remove DSP parameters that don't work commit | commitdiff | tree
2018-10-21 David Shahecp5: Add DSP blackboxes commit | commitdiff | tree
2018-10-20 Clifford WolfImprove read_verilog range out of bounds warning commit | commitdiff | tree
2018-10-20 Clifford WolfMerge pull request #674 from rubund/feature/svinterface... commit | commitdiff | tree
2018-10-20 Ruben UndheimRefactor code to avoid code duplication + added comments commit | commitdiff | tree
2018-10-20 Ruben UndheimSupport for SystemVerilog interfaces as a port in the... commit | commitdiff | tree
2018-10-20 Ruben UndheimFixed memory leak commit | commitdiff | tree
2018-10-19 Clifford WolfMerge pull request #673 from daveshah1/ecp5_improve commit | commitdiff | tree
2018-10-19 David Shahecp5: Sim model fixes commit | commitdiff | tree
2018-10-19 David Shahecp5: Add latch inference commit | commitdiff | tree
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram commit | commitdiff | tree
2018-10-19 David Shahmemory_bram: Reset make_outreg when growing read ports commit | commitdiff | tree
2018-10-19 Clifford WolfMerge pull request #671 from rafaeltp/master commit | commitdiff | tree
2018-10-19 Clifford WolfMerge pull request #670 from rubund/feature/basic_svint... commit | commitdiff | tree
2018-10-18 rafaeltpadding offset info to memories commit | commitdiff | tree
2018-10-18 rafaeltpadding offset info to memories commit | commitdiff | tree
2018-10-18 Ruben UndheimBasic test for checking correct synthesis of SystemVeri... commit | commitdiff | tree
2018-10-18 Clifford WolfUpdate ABC to git rev 14d985a commit | commitdiff | tree
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces commit | commitdiff | tree
2018-10-18 Clifford WolfMerge pull request #657 from mithro/xilinx-vpr commit | commitdiff | tree
2018-10-18 Clifford WolfMerge pull request #664 from tklam/ignore-verilog-protect commit | commitdiff | tree
2018-10-17 Clifford WolfUpdate ABC to git rev c5b48bb commit | commitdiff | tree
2018-10-17 Clifford WolfMinor code cleanups in liberty front-end commit | commitdiff | tree
2018-10-17 Clifford WolfMerge pull request #660 from tklam/parse-liberty-detect... commit | commitdiff | tree
2018-10-17 Clifford WolfMerge pull request #663 from aman-goel/master commit | commitdiff | tree
2018-10-17 Clifford WolfMerge pull request #658 from daveshah1/ecp5_bram commit | commitdiff | tree
2018-10-17 Clifford WolfMerge pull request #641 from tklam/master commit | commitdiff | tree
2018-10-17 Clifford WolfMerge pull request #638 from udif/pr_reg_wire_error commit | commitdiff | tree
2018-10-16 Clifford WolfWe have 2018 now commit | commitdiff | tree
2018-10-16 Clifford WolfAfter release is before release commit | commitdiff | tree
2018-10-16 Clifford WolfMerge branch 'yosys-0.8-rc' commit | commitdiff | tree
2018-10-16 Clifford WolfYosys 0.8 yosys-0.8 commit | commitdiff | tree
2018-10-16 argamaignore protect endprotect commit | commitdiff | tree
2018-10-16 Clifford WolfUpdate command reference manual commit | commitdiff | tree
2018-10-16 David Shahecp5: Disable LSR inversion commit | commitdiff | tree
2018-10-15 Aman GoelMinor update commit | commitdiff | tree
2018-10-13 Ruben UndheimHandle FIXME for modport members without type directly... commit | commitdiff | tree
2018-10-13 Ruben UndheimDocumentation improvements etc. commit | commitdiff | tree
2018-10-13 argamadetect ff/latch before processing other nodes commit | commitdiff | tree
2018-10-13 tklamstop check_signal_in_fanout from traversing FFs commit | commitdiff | tree
2018-10-13 tklamstop check_signal_in_fanout from traversing FFs commit | commitdiff | tree
2018-10-13 tklamMerge branch 'master' of https://github.com/YosysHQ... commit | commitdiff | tree
2018-10-12 Ruben UndheimFix build error with clang commit | commitdiff | tree
2018-10-12 Ruben UndheimSupport for 'modports' for System Verilog interfaces commit | commitdiff | tree
2018-10-12 Ruben UndheimSynthesis support for SystemVerilog interfaces commit | commitdiff | tree
2018-10-12 David ShahBRAM improvements commit | commitdiff | tree
2018-10-10 David Shahecp5: Adding BRAM maps for all size options commit | commitdiff | tree
2018-10-10 David Shahecp5: First BRAM type maps successfully commit | commitdiff | tree
2018-10-10 David Shahecp5: Script for BRAM IO connections commit | commitdiff | tree
2018-10-09 David Shahecp5: Adding BRAM initialisation and config commit | commitdiff | tree
2018-10-08 Tim 'mithro... xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. commit | commitdiff | tree
2018-10-07 Clifford WolfImprove Verific importer blackbox handling commit | commitdiff | tree
2018-10-05 David Shahecp5: Add blackbox for DP16KD commit | commitdiff | tree
2018-10-05 Clifford WolfMerge pull request #651 from ARandomOWL/stdcells_fix commit | commitdiff | tree
2018-10-05 Clifford WolfAdd "write_edif -attrprop" commit | commitdiff | tree
2018-10-05 Clifford WolfMerge pull request #654 from mithro/patch-1 commit | commitdiff | tree
2018-10-05 Clifford WolfFix compiler warning in verific.cc commit | commitdiff | tree
2018-10-05 Tim AnsellFix misspelling in issue_template.md commit | commitdiff | tree
2018-10-04 Adrian WheeldonFix IdString M in setup_stdcells() commit | commitdiff | tree
2018-10-04 Clifford WolfAdd inout ports to cells_xtra.v commit | commitdiff | tree
2018-10-04 Clifford WolfMerge pull request #650 from mithro/patch-1 commit | commitdiff | tree
2018-10-03 Tim Ansellxilinx: Adding missing inout IO port to IOBUF commit | commitdiff | tree
2018-10-03 tklamMerge branch 'master' of https://github.com/YosysHQ... commit | commitdiff | tree
2018-10-02 Clifford WolfMerge pull request #645 from daveshah1/ecp5_dram_fix commit | commitdiff | tree
2018-10-02 Clifford WolfMerge pull request #646 from tomverbeure/issue594 commit | commitdiff | tree
2018-10-02 Tom VerbeureFix for issue 594. commit | commitdiff | tree
2018-10-01 Aman GoelUpdate to .smv backend commit | commitdiff | tree
2018-10-01 Dan GisselquistAdd read_verilog $changed support commit | commitdiff | tree
2018-10-01 David Shahecp5: Don't map ROMs to DRAM commit | commitdiff | tree
2018-10-01 Aman GoelMerge pull request #4 from YosysHQ/master commit | commitdiff | tree
2018-09-30 Clifford WolfMerge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys commit | commitdiff | tree
2018-09-30 Clifford WolfFix handling of $past 2nd argument in read_verilog commit | commitdiff | tree
2018-09-28 Clifford WolfMerge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys commit | commitdiff | tree
2018-09-28 Clifford WolfUpdate to v2 YosysVS template commit | commitdiff | tree
2018-09-26 tklamfix bug: pass by reference commit | commitdiff | tree
2018-09-26 TK LamFix issue #639 commit | commitdiff | tree
2018-09-24 Udi FinkelsteinFixed issue #630 by fixing a minor typo in the previous... commit | commitdiff | tree
2018-09-24 Clifford WolfAdd "read_verilog -noassert -noassume -assert-assumes" commit | commitdiff | tree
2018-09-23 Clifford WolfAdded support for ommited "parameter" in Verilog-2001... commit | commitdiff | tree
2018-09-23 Clifford WolfMerge branch 'master' of https://github.com/mmicko... commit | commitdiff | tree
2018-09-23 Clifford WolfUpdate CHANGELOG commit | commitdiff | tree
2018-09-21 Miodrag Milanovicadded prefix to FDirection constants, fixing windows... commit | commitdiff | tree
2018-09-21 Clifford WolfUpdate CHANGLELOG commit | commitdiff | tree
2018-09-21 Clifford WolfUpdate Changelog commit | commitdiff | tree
2018-09-19 Clifford WolfMerge pull request #633 from mmicko/master commit | commitdiff | tree
2018-09-19 Clifford WolfMerge pull request #631 from acw1251/master commit | commitdiff | tree
2018-09-19 Miodrag MilanovicFix Cygwin build and document needed packages commit | commitdiff | tree
2018-09-18 acw1251Fixed typo in "verilog_write" help message commit | commitdiff | tree
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