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openpower-isa.git
2022-01-09 Dmitry Selyutinsv_binutils: discard VHDL stuff in comments commit | commitdiff | tree
2022-01-09 Dmitry Selyutinsv_binutils: calculate reserved bits commit | commitdiff | tree
2022-01-09 Dmitry Selyutinsv_binutils: reorder declarations commit | commitdiff | tree
2022-01-09 Dmitry Selyutinsv_binutils: print opcode as hexadecimal commit | commitdiff | tree
2022-01-06 Jacob Lifshayadd grev[w][i] instructions commit | commitdiff | tree
2022-01-06 Jacob Lifshayformat code commit | commitdiff | tree
2022-01-06 Jacob Lifshayadd stand-alone simulator bitmanip test commit | commitdiff | tree
2022-01-06 Luke Kenneth... add tlbsync and wait as NOPs commit | commitdiff | tree
2022-01-05 Luke Kenneth... add eieio instruction as a NOP to minor 31 csv commit | commitdiff | tree
2022-01-05 Luke Kenneth... add lbzcix instruction which had been completely forgot... commit | commitdiff | tree
2022-01-05 Dmitry Selyutinsv_binutils: introduce real opcode class commit | commitdiff | tree
2022-01-05 Dmitry Selyutinsv_binutils: parse CSVs directly commit | commitdiff | tree
2022-01-05 Dmitry Selyutinsv_binutils: support basic header generation commit | commitdiff | tree
2022-01-05 Dmitry Selyutinsv_binutils: introduce code generator class commit | commitdiff | tree
2022-01-05 Dmitry Selyutinsv_binutils: use stdin as input stream commit | commitdiff | tree
2022-01-05 Dmitry Selyutinsv_binutils: introduce helper classes commit | commitdiff | tree
2022-01-03 Luke Kenneth... copy over msr and rename cia to nia in PowerDecoder2 commit | commitdiff | tree
2021-12-28 Cesar StraussAdd an inorder flag to pspec commit | commitdiff | tree
2021-12-27 Luke Kenneth... add empty default_mem for running without MMU commit | commitdiff | tree
2021-12-27 Luke Kenneth... whoops wrong parameter name commit | commitdiff | tree
2021-12-27 Luke Kenneth... quick attempt to fix test_decoder_gas.py (did not work) commit | commitdiff | tree
2021-12-27 Mikolaj Wielgusbool() is !!() for integers commit | commitdiff | tree
2021-12-27 Mikolaj WielgusAdd missing parentheses for explicit operator precedence commit | commitdiff | tree
2021-12-26 Luke Kenneth... add very basic PowerDecode2 test which at least gets... commit | commitdiff | tree
2021-12-26 Luke Kenneth... a few extra things discovered needing c syntax not... commit | commitdiff | tree
2021-12-26 Mikolaj WielgusGive human-readable names to slots, run functions and... commit | commitdiff | tree
2021-12-25 Mikolaj WielgusPut CRTL CFFI modules in crtl dir commit | commitdiff | tree
2021-12-25 Dmitry Selyutinsv_binutils: provide small comment on regex commit | commitdiff | tree
2021-12-25 Dmitry Selyutinsv_binutils: introduce entry dataclass commit | commitdiff | tree
2021-12-24 Luke Kenneth... clear memory is optional commit | commitdiff | tree
2021-12-24 Luke Kenneth... whoops forgot to put the copy of the wb_get memory... commit | commitdiff | tree
2021-12-23 Luke Kenneth... code cleanup / comments commit | commitdiff | tree
2021-12-23 Luke Kenneth... repeat power decode test to check performance commit | commitdiff | tree
2021-12-23 Luke Kenneth... bit of a tidyup of crtl: commit | commitdiff | tree
2021-12-23 Luke Kenneth... add load-store byte-reverse 64-bit unit test commit | commitdiff | tree
2021-12-23 Mikolaj WielgusAdd CRTL templates commit | commitdiff | tree
2021-12-23 Mikolaj WielgusGive unique names to CRTL-generated modules commit | commitdiff | tree
2021-12-23 Mikolaj WielgusMove "pending" set to C commit | commitdiff | tree
2021-12-22 Mikolaj WielgusMake _PySignalState CRTL-aware commit | commitdiff | tree
2021-12-21 Luke Kenneth... take a copy of the wb_get memory and then for each... commit | commitdiff | tree
2021-12-21 Luke Kenneth... ISACaller (actually RADIXMMU) only do virtual memory... commit | commitdiff | tree
2021-12-20 Mikolaj WielgusGenerate variable declaration in some missing places commit | commitdiff | tree
2021-12-20 Luke Kenneth... create header/footer for crtl code-generation commit | commitdiff | tree
2021-12-20 Luke Kenneth... whoops forgot to trap if non-execute (instruction)... commit | commitdiff | tree
2021-12-19 Luke Kenneth... TODO notes for executing ISACaller Invalid Instruction... commit | commitdiff | tree
2021-12-19 Luke Kenneth... pass the mode (LOAD,EXECUTE,STORE) through ISACaller... commit | commitdiff | tree
2021-12-19 Luke Kenneth... add "stop at pc" argument to TestCase, commit | commitdiff | tree
2021-12-19 Dmitry Selyutinsv/binutils.py: provide sketch sv_decode.vhdl converter commit | commitdiff | tree
2021-12-19 Luke Kenneth... save mmu simulation to different gtkwave file in TestRu... commit | commitdiff | tree
2021-12-18 Luke Kenneth... bit more verbose info about number of instructions run commit | commitdiff | tree
2021-12-18 Luke Kenneth... use new core domain variable in TestRunnerBase commit | commitdiff | tree
2021-12-18 Luke Kenneth... update comments in wb_get commit | commitdiff | tree
2021-12-18 Luke Kenneth... ooo annoying, it is actually icache.ibus commit | commitdiff | tree
2021-12-18 Luke Kenneth... whoops error in accessing icache.ibus which is an inter... commit | commitdiff | tree
2021-12-17 Mikolaj WielgusCall the simulator-generated C using the CFFI commit | commitdiff | tree
2021-12-16 Luke Kenneth... bug where t1 was set to zero but s2 was not in imdct36_... commit | commitdiff | tree
2021-12-16 Luke Kenneth... start/stop wb_get in TestRunnerBase, otherwise it never... commit | commitdiff | tree
2021-12-15 Luke Kenneth... must read off of ibus in wb_get TestRunnerBase commit | commitdiff | tree
2021-12-14 Mikolaj WielgusAdd CFFI as dependency commit | commitdiff | tree
2021-12-13 Tobias Platenadd namedtuple MSRSpec commit | commitdiff | tree
2021-12-12 Luke Kenneth... copy over fake OP_FETCH_FAILED and instruction on... commit | commitdiff | tree
2021-12-12 Luke Kenneth... enable mmu_cache_wb for wb_get mode in TestRunnerBase commit | commitdiff | tree
2021-12-12 Luke Kenneth... add pretty-print of MMU memory to be used for a TestRun... commit | commitdiff | tree
2021-12-11 Luke Kenneth... remove ROTL64(1, idx), just use TLI[7-idx] it is shorte... commit | commitdiff | tree
2021-12-11 Luke Kenneth... use concat in ternlogi to reduce code size commit | commitdiff | tree
2021-12-10 Jacob Lifshayadd ternlogi to SVP64Asm commit | commitdiff | tree
2021-12-10 Jacob Lifshayformat code commit | commitdiff | tree
2021-12-10 Jacob Lifshaychange ternlogi to not have Rc field commit | commitdiff | tree
2021-12-10 Jacob Lifshayadd .gitignore to ignore the generated vhdl commit | commitdiff | tree
2021-12-09 Luke Kenneth... add I-Cache wishbone bus to wb_get when MMU and ROM... commit | commitdiff | tree
2021-12-09 Luke Kenneth... add warning about creation of "-.csv" which indicates... commit | commitdiff | tree
2021-12-09 Luke Kenneth... add FAST SPRs temporarily to power_enums commit | commitdiff | tree
2021-12-09 Jacob Lifshaymake ternlogi tests run commit | commitdiff | tree
2021-12-09 Jacob Lifshayrename ternaryi to ternlogi commit | commitdiff | tree
2021-12-09 Jacob Lifshayadd initial ternlogi pseudo-code commit | commitdiff | tree
2021-12-08 Luke Kenneth... add instr_fault to PowerDecoder2 commit | commitdiff | tree
2021-12-08 Luke Kenneth... whitespace commit | commitdiff | tree
2021-12-08 Luke Kenneth... code-comments for LDSTException.instr_fault commit | commitdiff | tree
2021-12-08 Luke Kenneth... add an on_Display function which is being used by some... commit | commitdiff | tree
2021-12-08 Luke Kenneth... found a way to print out the names of the signals commit | commitdiff | tree
2021-12-08 Luke Kenneth... absolute import again commit | commitdiff | tree
2021-12-08 Luke Kenneth... use full-path imports (so we know where they come from) commit | commitdiff | tree
2021-12-08 Mikolaj WielgusWIP: Output C instead of Python for Nmigen simulation commit | commitdiff | tree
2021-12-08 Mikolaj WielgusSource Nmigen simulator from this repository commit | commitdiff | tree
2021-12-07 Luke Kenneth... whoops wrong number commit | commitdiff | tree
2021-12-07 Luke Kenneth... add OP_FETCH_FAILED micro-op commit | commitdiff | tree
2021-12-07 Jacob Lifshayfix broken url commit | commitdiff | tree
2021-12-05 Tobias Platenfix microwatt_mmu and and wishbone_memory output in... commit | commitdiff | tree
2021-12-05 Luke Kenneth... connect to dcache.bus standard interface when using... commit | commitdiff | tree
2021-12-05 Luke Kenneth... correct import of wb_get function commit | commitdiff | tree
2021-12-04 Luke Kenneth... add name parameter to wb_get commit | commitdiff | tree
2021-12-04 Luke Kenneth... add wb_get function for emulating wishbone interface commit | commitdiff | tree
2021-12-04 Luke Kenneth... raise a MemException in ISACaller RADIXMMU commit | commitdiff | tree
2021-12-04 Luke Kenneth... enable MMU in SimRunner if requested. now HDL and... commit | commitdiff | tree
2021-12-04 Luke Kenneth... test in SimState for access to RADIX memory, bypass... commit | commitdiff | tree
2021-12-03 Luke Kenneth... add a namedtuple LDSTExceptionTuple which allows obtaining commit | commitdiff | tree
2021-12-03 Luke Kenneth... add link to exceptions in gtkw traces commit | commitdiff | tree
2021-12-02 Luke Kenneth... regspec_decode_write now stores the decoded write info... commit | commitdiff | tree
2021-12-02 Luke Kenneth... specify length in RegDecodeInfo explicitly so that... commit | commitdiff | tree
2021-12-02 Luke Kenneth... use namedtuple in get_rdflags commit | commitdiff | tree
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