yosys.git
2017-07-22 Clifford WolfAdd error for cell output ports that are connected...
2017-07-22 Clifford WolfAdd some simple SVA test cases for future Verific work
2017-07-22 Clifford WolfImprove docs for verific bindings, add simply sby example
2017-07-21 Clifford WolfFix handling of empty cell port assignments (i.e. ignor...
2017-07-21 Clifford WolfFix "read_blif -wideports" handling of cells with wide...
2017-07-21 Clifford WolfAdd a paragraph about pre-defined macros to read_verilo...
2017-07-21 Clifford WolfAdd verilator support to testbenches generated by yosys...
2017-07-18 Clifford WolfChange intptr_t to uintptr_t in hashlib.h
2017-07-18 Clifford WolfMerge pull request #363 from rqou/master
2017-07-17 Robert Oumakefile: Add the option to use libtermcap
2017-07-17 Robert OuFix build warnings for win64
2017-07-14 Clifford WolfAdd $alu to list of supported cells for "stat -width"
2017-07-12 Clifford WolfGenerate FSM-style testbenches in smtbmc
2017-07-11 Clifford WolfFix the fixed handling of x-bits in EDIF back-end
2017-07-11 Clifford WolfFix handling of x-bits in EDIF back-end
2017-07-10 Clifford WolfAdd attributes and parameter support to JSON front-end
2017-07-10 Clifford WolfAdd techlibs/xilinx/lut2lut.v
2017-07-08 Clifford WolfAdd JSON front-end
2017-07-07 Clifford WolfChange s/asserts/assertions/ in yosys-smtbmc log messages
2017-07-07 Clifford WolfAdd "yosys-smtbmc --presat"
2017-07-05 Clifford WolfFix generation of multiple outputs for same AIG node...
2017-07-05 Clifford WolfAdd write_table command
2017-07-04 Clifford WolfAdd Verific Release information to log
2017-07-03 Clifford WolfFix some c++ clang compiler errors
2017-07-03 Clifford WolfApply minor coding style changes to coolrunner2 target
2017-07-03 Clifford WolfMerge pull request #352 from rqou/master
2017-07-03 Clifford WolfMerge pull request #356 from set-soft/clean-test
2017-07-03 Clifford WolfMerge pull request #355 from set-soft/exclude_TBUF_merge
2017-07-03 Salvador E... Added the test outputs to the clean target
2017-07-03 Salvador E... Excluded $_TBUF_ from opt_merge pass
2017-07-03 Clifford WolfRemove unneeded delays in smtbmc vlogtb
2017-07-03 Clifford WolfInclude output ports with constant driver in AIGER...
2017-07-01 Clifford WolfAdd "yosys-smtbmc --vlogtb-top"
2017-07-01 Clifford WolfFix and_or_buffer optimization in opt_expr for signed...
2017-07-01 Clifford WolfFix smtbmc vlogtb bug in $anyseq handling
2017-06-30 Clifford WolfAdd "design -import"
2017-06-30 Clifford WolfAdd chtype command
2017-06-30 Clifford WolfAdd $tribuf to opt_merge blacklist
2017-06-27 Clifford WolfMerge pull request #353 from azonenberg/master
2017-06-26 Robert Oucoolrunner2: Add a few more primitives
2017-06-26 Robert Oucoolrunner2: Initial mapping of latches
2017-06-26 Robert Oucoolrunner2: Initial mapping of DFFs
2017-06-26 Robert Oucoolrunner2: Remove redundant INVERT_PTC
2017-06-26 Robert Oucoolrunner2: Remove debug prints
2017-06-26 Robert Oucoolrunner2: Correctly handle $_NOT_ after $sop
2017-06-26 Robert Oucoolrunner2: Also construct the XOR cell in the macrocell
2017-06-26 Robert Oucoolrunner2: Initial techmapping for $sop
2017-06-24 Andrew Zonenberggreenpak4_counters: Changed generation of primitive...
2017-06-24 Robert Oucoolrunner2: Initial commit
2017-06-20 Clifford WolfFix handling of init values in "abc -dff" and "abc...
2017-06-20 Clifford WolfFix history namespace collision
2017-06-20 Clifford WolfStore command history when terminating with an error
2017-06-20 Clifford WolfSwitched abc "clock domain not found" error to log_cmd_...
2017-06-07 Clifford WolfFix generation of vlogtb output in yosys-smtbmc for...
2017-06-01 Clifford WolfFix handling of Verilog ~& and ~| operators
2017-05-31 Clifford WolfUpdate ABC to hg rev efbf7f13ea9e
2017-05-31 Clifford WolfAdd dff2ff.v techmap file
2017-05-30 Clifford WolfFix AIGER back-end for multiple symbols per input/latch...
2017-05-28 Clifford WolfAdd "setundef -anyseq"
2017-05-28 Clifford WolfImprove write_aiger handling of unconnected nets and...
2017-05-27 Clifford WolfChange default smt2 solver to yices (Yices 2 has switch...
2017-05-24 Clifford WolfAdd aliases for common sets of gate types to "abc -g"
2017-05-23 Clifford WolfAdd examples/osu035
2017-05-23 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-05-23 Clifford WolfMerge pull request #346 from azonenberg/master
2017-05-23 Andrew Zonenberggreenpak4_counters: Added support for parallel output...
2017-05-17 Clifford WolfAdd workaround for CBMC bug to SimpleC back-end
2017-05-17 Clifford WolfEnable readline and tcl in mxe builds
2017-05-17 Clifford WolfAdd missing AndnotGate() and OrnotGate() declarations...
2017-05-17 Clifford WolfAdd $_ANDNOT_ and $_ORNOT_ gates
2017-05-16 Clifford WolfAdd <modname>_init() function generator to simpleC...
2017-05-16 Clifford WolfImprove simplec back-end
2017-05-15 Clifford WolfImprove simplec back-end
2017-05-14 Clifford WolfImprove simplec back-end
2017-05-13 Clifford WolfImprove simplec back-end
2017-05-12 Clifford WolfImprove simplec back-end
2017-05-12 Clifford WolfAdded support for more gate types to simplec back-end
2017-05-12 Clifford WolfAdd first draft of simple C back-end
2017-05-11 Clifford WolfUpdate ABC to hg rev e79576e10d72
2017-05-08 Clifford WolfFix boolector support in yosys-smtbmc
2017-04-30 Clifford WolfAdd support for localparam in module header
2017-04-28 Clifford WolfFix equiv_simple, old behavior now available with ...
2017-04-26 Clifford WolfAdd support for `resetall compiler directive
2017-04-12 Clifford WolfReplace CRLF line endings with LF in de2i.qsf (quartus...
2017-04-12 Larry DoolittleSquelch trailing whitespace
2017-04-07 Clifford WolfAdd MAX10 and Cyclone IV items to CHANGELOG
2017-04-07 Clifford WolfMerge pull request #337 from dh73/master
2017-04-06 dh73Add initial support for both MAX10 and Cyclone IV ...
2017-04-05 Clifford WolfAdd ConstEval defaultval feature
2017-04-05 Clifford WolfFix gcc compiler warning
2017-03-28 Clifford WolfAdd front-end detection for *.tcl files
2017-03-27 Clifford WolfAdd minisat 00_PATCH_typofixes.patch
2017-03-27 Clifford WolfRemove use of <fpu_control.h> in minisat
2017-03-20 Clifford WolfAdd "write_smt2 -stdt" mode
2017-03-19 Clifford WolfAdd generation of logic cells to EDIF back-end runtest.py
2017-03-19 Clifford WolfFix EDIF: portRef member 0 is always the MSB bit
2017-03-18 Clifford WolfAdd simple EDIF test case generator and checker
2017-03-14 Clifford WolfFix verilog pre-processor for multi-level relative...
2017-03-04 Clifford WolfImprove smt2 encodings of assert/assume/cover, better...
2017-03-02 Clifford WolfAdd write_aiger $anyseq support
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