yosys.git
2019-12-27 Eddie HungConsistency
2019-12-27 Eddie HungCope with abc9_arrival as string
2019-12-27 Eddie HungUpdate some abc9_arrival times, add abc9_required times
2019-12-25 Miodrag Milanovicfixed invalid char
2019-12-25 Marcin Kościelnickiiopadmap: Emit tristate buffers with const OE for some...
2019-12-25 Marcin KościelnickiMerge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
2019-12-25 Marcin KościelnickiMinor nit fixes
2019-12-23 Eddie HungAdd DSP cascade tests
2019-12-23 Eddie HungFix OPMODE for PCIN->PCOUT cascades in xc6s, check...
2019-12-23 Eddie HungFix CEA/CEB check
2019-12-23 Eddie HungFix checking CE[AB] and for direct connections
2019-12-23 Eddie HungSupport unregistered cascades for A and B inputs
2019-12-23 Eddie HungAdd DSP48A* PCOUT -> PCIN cascade support
2019-12-23 Marcin Kościelnickixilinx: Test our DSP48A/DSP48A1 simulation models.
2019-12-22 Marcin Kościelnickixilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-20 Eddie HungMerge pull request #1588 from YosysHQ/eddie/xaiger_cleanup
2019-12-20 Eddie HungAdd abc9_arrival times for RAM{32,64}M
2019-12-20 Eddie HungAdd RAM{32,64}M to abc9_map.v
2019-12-20 Eddie HungPut specify/endspecify inside ``
2019-12-20 Eddie HungMerge pull request #1585 from YosysHQ/eddie/fix_abc9_lut
2019-12-20 Eddie Hungwrite_xaiger: only instantiate each whitebox cell type...
2019-12-20 Eddie HungMerge pull request #1587 from YosysHQ/revert-1558-eddie...
2019-12-20 Eddie HungRevert "Optimise write_xaiger"
2019-12-20 Graham EdgecombeFix linking with Python 3.8
2019-12-20 Graham EdgecombeAdd PYTHON_CONFIG variable to the Makefile
2019-12-19 Eddie HungMerge pull request #1581 from YosysHQ/clifford/fix1565
2019-12-19 Eddie HungMerge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
2019-12-19 Eddie HungMerge pull request #1569 from YosysHQ/eddie/fix_1531
2019-12-19 Eddie HungMerge pull request #1571 from YosysHQ/eddie/fix_1570
2019-12-19 Marcin Kościelnickixilinx: Add simulation models for remaining CLB primitives.
2019-12-19 Marcin Kościelnickixilinx_dffopt: Keep order of LUT inputs.
2019-12-18 Eddie HungInterpret "abc9 -lut" as lut string only if [0-9:]
2019-12-18 Eddie HungAdd "scratchpad" to CHANGELOG
2019-12-18 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-12-18 David ShahMerge pull request #1563 from YosysHQ/dave/async-prld
2019-12-18 Eddie HungMerge pull request #1572 from nakengelhardt/scratchpad_pass
2019-12-18 Eddie HungMerge pull request #1584 from YosysHQ/mwk/xilinx-flaky...
2019-12-18 Marcin Kościelnickitests/xilinx: fix flaky mux test
2019-12-18 Marcin Kościelnickixilinx: Add xilinx_dffopt pass (#1557)
2019-12-18 Marcin Kościelnickixilinx: Improve flip-flop handling.
2019-12-18 Clifford WolfSend people to symbioticeda.com instead of verific.com
2019-12-18 N. Engelhardtuse extra_args
2019-12-17 Clifford WolfFix sim for assignments with lhs<rhs size, fixes #1565
2019-12-17 Eddie HungCleanup
2019-12-17 Eddie HungMerge pull request #1574 from YosysHQ/eddie/xilinx_lutram
2019-12-17 Eddie HungMerge pull request #1521 from dh73/diego/memattr
2019-12-17 Eddie HungEnforce non-existence
2019-12-16 Eddie HungUpdate doc
2019-12-16 Eddie HungAdd another test
2019-12-16 Eddie HungMore sloppiness, thanks @dh73 for spotting
2019-12-16 Eddie HungAccidentally commented out tests
2019-12-16 Eddie HungAdd unconditional match blocks for force RAM
2019-12-16 Eddie HungOops
2019-12-16 Eddie HungMerge blockram tests
2019-12-16 Eddie HungUpdate xc7/xcu bram rules
2019-12-16 Eddie HungImplement 'attributes' grammar
2019-12-16 Eddie HungMerge branch 'diego/memattr' of https://github.com...
2019-12-16 Eddie HungMerge branch 'eddie/xilinx_lutram' of github.com:YosysH...
2019-12-16 Eddie HungPopulate DID/DOD even if unused
2019-12-16 Eddie HungRename *RAM{32,64}M rules to RAM{32X2,64X1}Q
2019-12-16 Diego HFixing compiler warning/issues. Moving test script...
2019-12-16 N. Engelhardtadd assert option to scratchpad command
2019-12-16 Diego HRemoving fixed attribute value to !ramstyle rules
2019-12-16 Diego HMerging attribute rules into a single match block;...
2019-12-16 Eddie HungMerge pull request #1575 from rodrigomelo9/master
2019-12-16 Eddie HungMerge pull request #1577 from gromero/for-yosys
2019-12-16 Eddie HungMerge pull request #1578 from noopwafel/eqneq-debug
2019-12-15 Alyssa MilburnFix opt_expr.eqneq.cmpzero debug print
2019-12-13 Diego HRefactoring memory attribute matching based on IEEE...
2019-12-13 Eddie HungMerge pull request #1533 from dh73/bram_xilinx
2019-12-13 Eddie HungDisable RAM16X1D test
2019-12-13 Eddie HungDisable RAM16X1D match rule; carry-over from LUT4 arches
2019-12-13 Eddie HungRAM64M8 to also have [5:0] for address
2019-12-13 Diego HRenaming BRAM memory tests for the sake of uniformity
2019-12-13 Rodrigo Alejandro... Fixed some missing "verilog_" in documentation
2019-12-13 N. Engelhardtadd periods and newlines to help message
2019-12-13 Eddie HungRemove extraneous synth_xilinx call
2019-12-13 Eddie HungAdd tests for these new models
2019-12-13 Eddie HungAdd RAM32X6SDP and RAM64X3SDP modes
2019-12-13 Eddie HungFix RAM64M model to have 6 bit address bus
2019-12-13 Eddie HungAdd #1460 testcase
2019-12-13 Eddie HungAdd memory rules for RAM16X1D, RAM32M, RAM64M
2019-12-13 Eddie HungRename memory tests to lutram, add more xilinx tests
2019-12-12 Diego HFixing citation in xc7_xcu_brams.txt file. Fixing RAMB3...
2019-12-12 Eddie Hungabc9_map.v: fix Xilinx LUTRAM
2019-12-12 Diego HAdding a note (TODO) in the memory_params.ys check...
2019-12-12 N. Engelhardtadd test and make help message more verbose
2019-12-12 Diego HUpdating RAMB36E1 thresholds. Adding test for both...
2019-12-12 Diego HMerge https://github.com/YosysHQ/yosys into bram_xilinx
2019-12-12 Eddie HungMake SV2017 compliant courtesy of @wsnyder
2019-12-12 N. Engelhardtadd a command to read/modify scratchpad contents
2019-12-12 Eddie HungStray log_dump
2019-12-12 Eddie HungPreserve size of $genval$-s in for loops
2019-12-12 Eddie HungAdd testcase
2019-12-12 Eddie HungUpdate README.md :: abc_ -> abc9_
2019-12-11 Eddie HungFix bitwidth mismatch; suppresses iverilog warning
2019-12-11 Gustavo Romeromanual: Fix text in Abstract section
2019-12-11 David ShahMerge pull request #1564 from ZirconiumX/intel_housekeeping
2019-12-10 Dan Ravensloftsynth_intel: a10gx -> arria10gx
2019-12-10 Dan Ravensloftsynth_intel: cyclone10 -> cyclone10lp
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