yosys.git
2015-08-17 Clifford WolfMerge pull request #72 from cseed/master
2015-08-17 Cotton SeedAdded .travis.yml.
2015-08-16 Clifford WolfAnother bugfix for ice40 and xilinx brams_init make...
2015-08-16 Clifford WolfFixed Makefile rules for generated share files
2015-08-16 Clifford WolfAdded $tribuf and $_TBUF_ sim models
2015-08-16 Clifford WolfAdded tribuf command
2015-08-16 Clifford WolfAdded $tribuf and $_TBUF_ cell types
2015-08-16 Clifford WolfFixed opt_clean handling of inout ports
2015-08-15 Clifford WolfFixed generation of smt2 concat statements
2015-08-14 Larry DoolittleFix version strings for out-of-tree builds
2015-08-14 Larry DoolittleAnother block of spelling fixes
2015-08-14 Larry DoolittleKeep gcc from complaining about uninitialized variables
2015-08-14 Clifford WolfRe-created command-reference-manual.tex, copied some...
2015-08-14 Clifford WolfSpell check (by Larry Doolittle)
2015-08-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-08-13 Clifford WolfMore ASCII encoding fixes
2015-08-13 Clifford WolfFixed CRLF line endings
2015-08-13 Clifford WolfSome ASCII encoding fixes (comments and docs) by Larry...
2015-08-12 Clifford WolfAdded "write_smt2 -regs"
2015-08-12 Clifford WolfFixed "make clean" for out-of-tree builds
2015-08-12 Clifford WolfAdjust makefiles to work with out-of-tree builds
2015-08-12 Clifford WolfImproved handling of "keep" attributes in hierarchical...
2015-08-12 Clifford WolfFixed hashlib for 64 bit int keys
2015-08-12 Clifford WolfAdded SMV back-end 'test_cells.sh' script
2015-08-12 Clifford WolfMerge pull request #70 from gaomy3832/bugfix
2015-08-11 Mingyu GaoRemove unused blackbox modules in opt_clean.
2015-08-11 Mingyu GaoBugfix for cell hash cache option in opt_share.
2015-08-11 Clifford WolfFixed handling of [a-fxz?] in decimal constants
2015-08-11 Clifford WolfAdded missing ct_all setup to opt_clean
2015-08-10 Mingyu GaoBugfix for cell hash cache option in opt_share.
2015-08-09 Clifford WolfUse MEMID as name for $mem cell
2015-08-06 Clifford WolfMerge pull request #69 from zeldin/master
2015-08-06 Marcus ComstedtAdded iCE40 WARMBOOT cell
2015-08-05 Clifford WolfRemove some very strange whitespace in btor.cc (by...
2015-08-05 Clifford WolfBugfix in SMV back-end for partially unassigned wires
2015-08-04 Clifford WolfAdded ENABLE_LIBYOSYS Makefile option
2015-08-04 Clifford WolfAdded $assert support to SMV back-end
2015-08-04 Clifford WolfAdded libyosys.so build
2015-08-01 Clifford WolfMerge pull request #68 from zeldin/master
2015-08-01 Marcus ComstedtAdd -noautowire option to verilog frontend
2015-07-31 Clifford WolfAdded WORDS parameter to $meminit
2015-07-30 Clifford WolfFixed flatten $meminit handling
2015-07-29 Clifford WolfImprovements in BLIF back-end
2015-07-29 Clifford WolfFixed nested mem2reg
2015-07-27 Clifford WolfDon't write a 17th memory bit in ice40/cells_sim (by...
2015-07-27 Clifford WolfFixed "check" command for inout ports
2015-07-25 Clifford WolfSome cleanups in opt_rmdff
2015-07-25 Clifford WolfAdded "miter -assert"
2015-07-25 Clifford WolfKeep modules with $assume (like $assert)
2015-07-24 Clifford WolfImproved $adff simplification
2015-07-20 Clifford WolfiCE40 DFF sim models: init Q regs to 0
2015-07-18 Clifford WolfFixed techmap processes error msg
2015-07-18 Clifford WolfAvoid tristate warning for blackbox ice40/cells_sim.v
2015-07-16 Clifford WolfSome fixes in "select" command
2015-07-10 Clifford WolfFixed YosysJS.create_worker() usage of this.url_prefix
2015-07-06 Clifford WolfImproved liberty file test case
2015-07-06 Clifford WolfUpdated ABC
2015-07-06 Clifford WolfDo not collect disabled $memwr cells
2015-07-04 Clifford WolfImproved YosysJS WebWorker API
2015-07-03 Clifford WolfBugfix in fsm_extract
2015-07-02 Clifford WolfAdded "synth -nofsm"
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-07-01 Clifford WolfAdded opt_const -clkinv
2015-06-30 Clifford WolfAdded logic-loop error handling to freduce
2015-06-29 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-06-29 Clifford WolfBugfix in chparam
2015-06-29 Clifford WolfAdded design->rename(module, new_name)
2015-06-28 Clifford WolfAdded YosysJS.create_worker()
2015-06-20 Clifford WolfiCE40: set min bram efficiency to 2%
2015-06-20 Clifford WolfUsing static mem size of 128 MB in emcc build
2015-06-19 Clifford WolfAdded init support to SMV back-end
2015-06-19 Clifford WolfProgress in SMV back-end
2015-06-19 Clifford WolfProgress in SMV back-end
2015-06-18 Clifford WolfProgress in SMV back-end
2015-06-17 Clifford WolfProgress in SMV back-end
2015-06-17 Clifford WolfAdded "rename -top new_name"
2015-06-17 Clifford WolfProgress in SMV back-end
2015-06-16 Clifford WolfProgress in SMV back-end
2015-06-15 Clifford WolfAdded "synth -nordff -noalumacc"
2015-06-15 Clifford WolfProgress in SMV back-end
2015-06-15 Clifford WolfProgress in SMV back-end
2015-06-14 Clifford WolfAdded "write_smv" skeleton
2015-06-14 Clifford WolfRemoved debug code from write_smt2
2015-06-14 Clifford WolfModernized memory_dff (and fixed a bug)
2015-06-14 Clifford WolfAdded "memory -nordff"
2015-06-14 Clifford WolfAdded write_smt2 -mem
2015-06-11 Clifford WolfMakefile fix for YosysJS build
2015-06-11 Clifford WolfFixed cstr_buf for std::string with small string optimi...
2015-06-11 Clifford WolfImprovements in cellaigs.cc and "json -aig"
2015-06-10 Clifford WolfAigMaker refactoring
2015-06-10 Clifford WolfAdded "json -aig"
2015-06-10 Clifford WolfRenamed "aig" to "aigmap"
2015-06-10 Clifford WolfFixed cellaigs port extending
2015-06-09 Clifford WolfAdded "aig" pass
2015-06-09 Clifford Wolfsynth_ice40 now flattens by default
2015-06-09 Clifford WolfAdded cellaigs API
2015-06-09 Clifford WolfMerge clock inverters in memory_dff
2015-06-09 Clifford WolfMerge branch 'verilog-backend-memV2' of github.com...
2015-06-08 luke whittlesey$mem cell in verilog backend : grouped writes by clock
2015-06-08 Clifford WolfFixed "avail_parameters" handling in module clone/copy
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