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gram.git
2020-07-10
Jean THOMAS
Fix formal checks for RefreshTimer
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2020-07-10
Jean THOMAS
Fix tests for _AntiStarvation
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2020-07-10
Jean THOMAS
Fix code styling
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2020-07-10
Jean THOMAS
Rename VCD file output
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2020-07-10
Jean THOMAS
Rename tests, add interleaved read/write test
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2020-07-10
Jean THOMAS
Implement a memory in the bank simulator, check for...
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2020-07-10
Jean THOMAS
Fix timings in simulation to prevent tDLLK errors
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2020-07-10
Jean THOMAS
Add POR start/end logging in simsoc testbench
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2020-07-09
Jean THOMAS
Make power-on delay signal synchronous
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2020-07-09
Jean THOMAS
Fix formatting in headless example
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2020-07-09
Jean THOMAS
Add test for SoC readout
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2020-07-09
Jean THOMAS
Disable Assert statements until they are natively suppo...
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2020-07-09
Jean THOMAS
Comment buggy assertions
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2020-07-09
Jean THOMAS
Add imports for Assert & Assume in FakePHY
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2020-07-09
Jean THOMAS
Fix counter reset condition bug
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2020-07-09
Jean THOMAS
Fix syntax in FakePHY assertions
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2020-07-09
Jean THOMAS
Use assertions as a temporary replacement for Display...
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2020-07-09
Jean THOMAS
Remove unused BitFlip
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2020-07-09
Jean THOMAS
Update build script to include software version
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2020-07-08
Jean THOMAS
Add temporary code for SoC tests with FakePHY
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2020-07-08
Jean THOMAS
Port FakePHY to nMigen
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2020-07-08
Jean THOMAS
Match ECPIX-5 DRAM parameters in Micron's model
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2020-07-08
Jean THOMAS
Import fake PHY from LiteDRAM (non functionnal ATM)
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2020-07-08
Jean THOMAS
Fix styling
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2020-07-08
Jean THOMAS
Add test case for AntiStarvation
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2020-07-08
Jean THOMAS
Fix bugs in _AntiStarvation
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2020-07-08
Jean THOMAS
Update memtest code
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2020-07-08
Jean THOMAS
Remove useless variables in _Steerer, ensure command...
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2020-07-08
Jean THOMAS
Make an Elaboratable out of the anti_starvation function
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2020-07-08
Jean THOMAS
Add links to various docs that have been helpful
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2020-07-08
Jean THOMAS
Drop YoWASP, build Yosys and SymbiYosys from source
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2020-07-08
Jean THOMAS
Fix dram_model path in .gitattributes
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2020-07-08
Jean THOMAS
Fix clock input
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2020-07-08
Jean THOMAS
cke => clk_en in SoC testbench
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2020-07-07
Jean THOMAS
Update cke => clk_en in test
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2020-07-07
Jean THOMAS
Fix code styling
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2020-07-07
Jean THOMAS
Fix code styling
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2020-07-07
Jean THOMAS
Replace cke with clk_en
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2020-07-07
Jean THOMAS
Fix CRG PLL parameters (fixing #23)
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2020-07-06
Jean THOMAS
Rename from cke to clk_en
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2020-07-06
Jean THOMAS
Make RefreshTimer fully synchronous (#24)
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2020-07-06
Jean THOMAS
Add write transactions in the simulation testbench
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2020-07-06
Jean THOMAS
Reduce amount of combinatorial statements to improve...
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2020-07-06
Jean THOMAS
Fix formal support in FHDLTestCase
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2020-07-03
Jean THOMAS
Remove Diamond install script
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2020-07-03
Jean THOMAS
Add SourceHut badge
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2020-07-03
Jean THOMAS
Add .gitattributes file
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2020-07-03
Jean THOMAS
Remove Diamond install as it only comes with models...
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2020-07-03
Jean THOMAS
Use CRG parameters that actually work on hardware
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2020-07-03
Jean THOMAS
Update CRG with parameters that work IRL
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2020-07-03
Jean THOMAS
Invert condition in runsimcrg.sh
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2020-07-03
Jean THOMAS
Remove remainings from TRELLIS_IO
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2020-07-03
Jean THOMAS
Check if YOSYS env var is set and use it as YOSYS execu...
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2020-07-03
Jean THOMAS
Use Yosys from YoWASP
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2020-07-03
Jean THOMAS
Fix permissions for simulation script
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2020-07-03
Jean THOMAS
Add simulation script into SourceHut builds
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2020-07-03
Jean THOMAS
Exclude DDRDLLA from tree
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2020-07-03
Jean THOMAS
Ensure dramsync runs at 100Mhz, sync2x at 200Mhz
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2020-07-03
Jean THOMAS
Remove DDRDLLA
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2020-07-03
Jean THOMAS
Add build script for SourceHut
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2020-07-03
Jean THOMAS
Add tests in DFI Injector for odt and reset signals
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2020-07-03
Jean THOMAS
Check for additional signals in phase injector at t=0
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2020-07-03
Jean THOMAS
Add DFI injector test case
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2020-07-03
Jean THOMAS
Update simulation gitignore
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2020-07-03
Jean THOMAS
Update gram simulation documentation
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2020-07-03
Jean THOMAS
Add cleaning pass
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2020-07-03
Jean THOMAS
Fix autopep8 madness
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2020-07-03
Jean THOMAS
Rework CRG simulation
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2020-07-03
Jean THOMAS
Externalize CRG into its own file
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2020-07-03
Jean THOMAS
Add devel doc
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2020-07-03
Jean THOMAS
Add test for Refresher
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2020-07-03
Jean THOMAS
Refactor generic_test execution
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2020-07-03
Jean THOMAS
Use spaces for indentation
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2020-07-03
Jean THOMAS
Add tests for core/refresher.py
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2020-07-03
Jean THOMAS
Removing reset=0 attribute as it is already the default...
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2020-07-02
Jean THOMAS
Use reset signal from dramsync instead of sync
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2020-07-02
Jean THOMAS
Make RefreshPostponer more similar to LiteDRAM's
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2020-07-02
Jean THOMAS
Fix RefreshPostponer output stuck to 1
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2020-07-02
Jean THOMAS
Flatten specific parts of the designs
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2020-07-02
Jean THOMAS
Add missing command issue strobe for ZQ calibration
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2020-07-02
Jean THOMAS
Remove PyYAML dependency
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2020-07-02
Jean THOMAS
Fix register addresses, add missing command_issue strobe
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2020-07-02
Jean THOMAS
Set names to prevent CSR/DomainRenamer incompatibility
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2020-07-02
Jean THOMAS
Add DDRDLLA patch
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2020-07-01
Jean THOMAS
Fix merge
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2020-07-01
Jean THOMAS
Rework indentation and add Wishbone tests
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2020-07-01
Jean THOMAS
Add Wishbone interaction code
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2020-07-01
Jean THOMAS
Add Wishbone interaction code
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2020-07-01
Jean THOMAS
Fix Iverilog simulation
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2020-07-01
Jean THOMAS
Generate ilang file
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2020-06-30
Jean THOMAS
Build nMigen gateware in a specific folder
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2020-06-30
Jean THOMAS
Remove LED code in CRG
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2020-06-30
Jean THOMAS
Remove Minerva dependency
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2020-06-30
Jean THOMAS
Applying #9044c10 changes in LiteDRAM (phy/ecp5ddrphy...
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2020-06-29
Jean THOMAS
Define simulation time as a parameter
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2020-06-29
Jean THOMAS
Define PLL's PHASELOADREG input
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2020-06-29
Jean THOMAS
Use -n option in vvp to enable CTRL+C
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2020-06-29
Jean THOMAS
Fix PLL instanciation code for CRG simulation
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2020-06-29
Jean THOMAS
Dump whole module
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2020-06-29
Jean THOMAS
Fix DQSBUFM floating DYNDELAY
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