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yosys.git
2021-10-25
Miodrag Milanovic
Compile option for enabling async load verific support
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2021-10-22
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2021-10-21
Marcelina Kościelnicka
Change implicit conversions from bool to Sig* to explicit.
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2021-10-21
Claire Xen
Merge pull request #3057 from YosysHQ/claire/verific_la...
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2021-10-21
Claire Xenia...
Fix verific.cc PRIM_DLATCH handling
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2021-10-21
Claire Xenia...
Initial Verific impoter support for {PRIM,WIDE_OPER...
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2021-10-21
Marcelina Kościelnicka
extract_reduce: Refactor and fix input signal construction.
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2021-10-21
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2021-10-20
Miodrag Milanovic
If verific have vhdl lib it is required by other libs
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2021-10-20
Miodrag Milanovic
Forgot to remove from main list
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2021-10-20
Miodrag Milanovic
Option to disable verific VHDL support
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2021-10-20
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2021-10-19
Claire Xenia...
Fixed Verific parser error in ice40 cell library
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2021-10-19
Miodrag Milanović
Merge pull request #3045 from galibert/master
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2021-10-19
Claire Xenia...
Fixes in vcdcd.pl for newer Perl versions
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2021-10-18
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2021-10-17
Paul Annesley
dfflegalize: remove redundant check for initialized...
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2021-10-17
Olivier Galibert
CycloneV: Add (passthrough) support for cyclonev_oscillator
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2021-10-17
Olivier Galibert
CycloneV: Add (passthrough) support for cyclonev_hps_in...
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2021-10-16
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2021-10-15
Claire Xen
Merge pull request #3044 from YosysHQ/micko/verific_bufif1
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2021-10-14
Miodrag Milanovic
Support PRIM_BUFIF1 primitive
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2021-10-12
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2021-10-11
Claire Xen
Merge pull request #3039 from YosysHQ/claire/verific_aldff
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2021-10-11
Claire Xenia...
Add Verific adffe/dffsre/aldffe FIXMEs
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2021-10-11
Claire Xen
Merge pull request #3040 from YosysHQ/micko/split_modul...
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2021-10-11
Claire Xen
Merge pull request #3041 from YosysHQ/mmicko/module_attr
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2021-10-10
Miodrag Milanovic
Import module attributes from Verific
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2021-10-09
Miodrag Milanovic
Split module ports, 20 per line
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2021-10-09
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2021-10-08
Claire Xenia...
Fixes and add comments for open FIXME items
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2021-10-08
Claire Xenia...
Add support for $aldff flip-flops to verific importer
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2021-10-08
Marcelina Kościelnicka
Fix a regression from #3035.
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2021-10-08
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2021-10-07
Marcelina Kościelnicka
FfData: some refactoring.
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2021-10-05
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2021-10-04
Miodrag Milanovic
verific set db_infer_set_reset_registers
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2021-10-03
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2021-10-02
Marcelina Kościelnicka
Hook up $aldff support in various passes.
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2021-10-02
Marcelina Kościelnicka
zinit: Refactor to use FfData.
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2021-10-02
Marcelina Kościelnicka
kernel/ff: Refactor FfData to enable FFs with async...
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2021-10-02
Marcelina Kościelnicka
Add $aldff and $aldffe: flip-flops with async load.
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2021-10-02
Zachary Snow
Specify minimum bison version 3.0+
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2021-10-02
Marcelina Kościelnicka
simplemap: refactor to use FfData.
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2021-09-28
Miodrag Milanović
Merge pull request #3017 from YosysHQ/claire/short_rtli...
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2021-09-28
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2021-09-27
Miodrag Milanovic
Prepare for next release cycle
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2021-09-27
Claire Xenia...
Add optimization to rtlil back-end for all-x parameter...
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2021-09-25
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2021-09-24
Claire Xen
Merge pull request #3014 from YosysHQ/claire/fix-vgtest
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2021-09-23
Zachary Snow
Fix TOK_ID memory leak in for_initialization
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2021-09-23
Claire Xenia...
Fix "make vgtest" so it runs to the end (but now it...
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2021-09-22
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2021-09-21
Zachary Snow
sv: support wand and wor of data types
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2021-09-21
Zachary Snow
verilog: fix multiple AST_PREFIX scope resolution issues
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2021-09-19
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2021-09-18
Miodrag Milanović
Merge pull request #3010 from the6p4c/master
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2021-09-17
the6p4c
Fix protobuf backend build dependencies
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2021-09-14
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2021-09-13
Marcelina Kościelnicka
verilog: Squash flex-triggered warning.
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2021-09-13
Miodrag Milanović
Updates for CHANGELOG (#2997)
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2021-09-11
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2021-09-10
Miodrag Milanović
Merge pull request #3001 from YosysHQ/claire/sigcheck
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2021-09-10
Claire Xenia...
Add additional check to SigSpec
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2021-09-10
Marcelina Kościelnicka
yosys-smtbmc: Fix reused loop variable.
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2021-09-10
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2021-09-09
Eddie Hung
abc9: make re-entrant (#2993)
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2021-09-09
Eddie Hung
abc9: holes module to instantiate cells with NEW_ID...
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2021-09-09
Eddie Hung
abc9: replace cell type/parameters if derived type...
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2021-09-03
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2021-09-02
Miodrag Milanovic
update required verific version
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2021-09-01
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2021-08-31
Zachary Snow
sv: support declaration in generate for initialization
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2021-08-31
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2021-08-30
Zachary Snow
sv: support declaration in procedural for initialization
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2021-08-30
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2021-08-29
kittennbfive
[ECP5] fix wrong link for syn_* attributes description...
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2021-08-23
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2021-08-22
ECP5-PCIe
Add DLLDELD
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2021-08-22
Marcelina Kościelnicka
opt_merge: Remove and reinsert init when connecting...
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2021-08-22
Marcelina Kościelnicka
opt_clean: Make the init attribute follow the FF's Q.
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2021-08-21
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2021-08-20
Pepijn de Vos
Gowin: deal with active-low tristate (#2971)
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2021-08-20
Miodrag Milanović
Merge pull request #2973 from YosysHQ/micko/optional_ex...
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2021-08-20
Miodrag Milanovic
Make Verific extensions optional
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2021-08-18
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2021-08-17
Sylvain Munaut
ice40: Fix typo in SB_CARRY specify for LP/UltraPlus
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2021-08-17
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2021-08-16
Marcelina Kościelnicka
kernel/mem: Remove old parameter when upgrading $mem...
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2021-08-15
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2021-08-14
Marcelina Kościelnicka
proc_prune: Make assign removal and promotion per-bit...
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2021-08-14
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2021-08-13
Rupert Swarbrick
Generate an RTLIL representation of bind constructs
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2021-08-13
Marcelina Kościelnicka
Add opt_mem_widen pass.
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2021-08-13
Marcelina Kościelnicka
memory_share: Add -nosat and -nowiden options.
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2021-08-13
Marcelina Kościelnicka
memory_dff: Recognize soft transparency logic.
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2021-08-13
Marcelina Kościelnicka
Add new opt_mem_priority pass.
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2021-08-13
Miodrag Milanović
Merge pull request #2932 from YosysHQ/mwk/logger-check...
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2021-08-13
Brett Witherspoon
sv: improve support for wire and var with user-defined...
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2021-08-13
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