yosys.git
2019-08-08 David ShahDSP48E1 sim model: add SIMD tests
2019-08-08 David ShahDSP48E1 model: test CE inputs
2019-08-08 David ShahDSP48E1 sim model: fix seq tests and add preadder tests
2019-08-08 David ShahDSP48E1 sim model: seq test working
2019-08-08 David ShahDSP48E1 sim model: Comb, no pre-adder, mode working
2019-08-08 David Shah[wip] sim model testing
2019-08-08 David Shah[wip] sim model testing
2019-08-07 David Shah[wip] DSP48E1 sim model improvements
2019-08-06 David Shah[wip] DSP48E1 sim model improvements
2019-08-06 David Shah[wip] DSP48E1 sim model improvements
2019-08-01 Eddie HungAdd comment about supporting $dffe in ice40_dsp
2019-08-01 Eddie HungPack P register properly
2019-08-01 Eddie HungTrim Y_WIDTH
2019-08-01 Eddie HungAdd DSP_SIGNEDONLY back
2019-08-01 Eddie HungDSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH
2019-08-01 Eddie HungChange $__softmul back to $mul
2019-08-01 Eddie HungCope with sign extension in mul2dsp
2019-08-01 Eddie HungRevert "Do not do sign extension in techmap; let packer...
2019-08-01 Eddie HungMerge remote-tracking branch 'origin/master' into xc7dsp
2019-08-01 Eddie HungFix B_WIDTH > DSP_B_MAXWIDTH case
2019-08-01 Eddie HungCO is sign extension only if signed multiplier
2019-08-01 Eddie HungFix typo
2019-08-01 Eddie HungMerge pull request #1236 from YosysHQ/eddie/xc6s_brams_map
2019-07-31 Eddie HungDo not compute sign bit if result is zero
2019-07-31 Eddie HungFor signed multipliers, compute sign bit separately...
2019-07-31 Eddie HungRestore old CO behaviour
2019-07-31 Eddie HungHelper: SigSpec::operator[] to accept negative indices
2019-07-31 Clifford WolfMerge pull request #1233 from YosysHQ/clifford/defer
2019-07-29 Eddie HungRST -> RSTBRST for RAMB8BWER
2019-07-29 Eddie HungMerge pull request #1228 from YosysHQ/dave/yy_buf_size
2019-07-29 David ShahMerge pull request #1234 from mmicko/fix_gzip_no_exist
2019-07-29 Miodrag MilanovicFix case when file does not exist
2019-07-29 Clifford WolfUpdate README to use "read" instead of "read_verilog"
2019-07-29 Clifford WolfCall "read_verilog" with -defer from "read"
2019-07-27 David ShahMerge pull request #1226 from YosysHQ/dave/gzip
2019-07-26 Eddie HungFix spacing
2019-07-26 Eddie HungUpdate test_autotb doc to reflect default value of...
2019-07-26 Eddie HungAdd doc for "test_autotb -seed" option
2019-07-26 Eddie HungPop the CO bit from O
2019-07-26 Eddie HungAllow adders/accumulators with 33 bits using CO output
2019-07-26 David ShahUpdate CHANGELOG
2019-07-26 David Shahverilog_lexer: Increase YY_BUF_SIZE to 65536
2019-07-26 David ShahFix frontend auto-detection for gzipped input
2019-07-26 David ShahAdd support for reading gzip'd input files
2019-07-25 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-07-25 Eddie HungBump abc to fix &mfs bug
2019-07-25 Clifford WolfMerge branch 'ZirconiumX-synth_intel_m9k'
2019-07-25 Clifford WolfMerge pull request #1218 from ZirconiumX/synth_intel_iopads
2019-07-25 Clifford WolfMerge pull request #1219 from jakobwenzel/objIterator
2019-07-25 Eddie HungMerge pull request #1224 from YosysHQ/xilinx_fix_ff
2019-07-25 Jakob Wenzelreplaced std::iterator with using statements
2019-07-25 David Shahxilinx: Fix missing cell name underscore in cells_map.v
2019-07-24 Eddie HungMerge pull request #1222 from koriakin/s6-example
2019-07-24 Eddie HungAdd copyright header, comment on cascade
2019-07-24 Marcin KoƛcielnickiAdd a simple example for Spartan 6
2019-07-24 Jakob Wenzelmade ObjectIterator extend std::iterator
2019-07-24 Dan Ravensloftintel: Make -noiopads the default
2019-07-23 Eddie HungEliminate warnings by sizing O correctly
2019-07-23 Eddie HungTypo for Y_WIDTH
2019-07-23 Eddie HungFix muxAB logic
2019-07-23 Eddie HungRemove debug print
2019-07-23 Eddie HungSimplify and fix for MACs
2019-07-23 Eddie HungFix typo
2019-07-23 Dan Ravensloftintel: Map M9K BRAM only on families that have it
2019-07-23 Eddie HungMerge pull request #1212 from YosysHQ/eddie/signed_ice4...
2019-07-22 Eddie HungFix spacing
2019-07-22 Eddie HungRemove debug
2019-07-22 Eddie HungPack hi and lo registers separately
2019-07-22 Eddie HungSigSpec::extract() to return as many bits as poss if...
2019-07-22 Eddie HungRename according to vendor doc TN1295
2019-07-22 Eddie HungPack Y register
2019-07-22 Eddie Hungopt and wreduce necessary for -dsp
2019-07-22 Eddie HungPack adders not just accumulators
2019-07-22 Eddie HungUse minimum sized width wires
2019-07-22 Eddie HungMerge pull request #1214 from jakobwenzel/astmod_clone
2019-07-22 Jakob Wenzelinitialize noblackbox and nowb in AstModule::clone
2019-07-20 Clifford WolfAdd "stat -tech cmos"
2019-07-20 Eddie HungRestore old ffY behaviour
2019-07-20 Eddie HungCleanup
2019-07-20 Eddie HungIndirection via $__soft_mul
2019-07-19 Eddie HungDo not do sign extension in techmap; let packer do it
2019-07-19 Eddie HungMerge remote-tracking branch 'origin/eddie/wreduce_add...
2019-07-19 Eddie HungAdd another test
2019-07-19 Eddie HungDo not access beyond bounds
2019-07-19 Eddie HungAdd an SigSpec::at(offset, defval) convenience method
2019-07-19 Eddie HungWrap A and B in sigmap
2019-07-19 Eddie HungRemove "top" from message
2019-07-19 Eddie HungMerge remote-tracking branch 'origin/eddie/wreduce_add...
2019-07-19 Eddie HungAlso optimise MSB of $sub
2019-07-19 Eddie HungAdd one more test with trimming Y_WIDTH of $sub
2019-07-19 Eddie HungBe more explicit
2019-07-19 Eddie Hungwreduce for $sub
2019-07-19 Eddie HungAdd tests for sub too
2019-07-19 Eddie HungAdd test
2019-07-19 Eddie HungSigSpec::extract to take negative lengths
2019-07-19 Eddie HungDo not $mul -> $__mul if A and B are less than maxwidth
2019-07-19 Eddie HungAdd DSP_MINWIDTH=11 for ice40 since ice40_dsp uses...
2019-07-19 Eddie HungAdd a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH...
2019-07-19 Eddie HungFine tune ice40_dsp.pmg, add support for packing subset...
2019-07-19 Eddie HungAdd support for ice40 signed multipliers
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