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yosys.git
2019-02-17
Eddie Hung
write_aiger -O to write dummy output as __dummy_o__
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2019-02-16
Eddie Hung
abc9 to handle comb loops, cope with constant outputs...
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2019-02-16
Eddie Hung
read_aiger to disable log_debug
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2019-02-16
Eddie Hung
expose command to not skip 'internal' wires beginning...
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2019-02-16
Eddie Hung
read_xaiger() to use f.read() not readsome()
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2019-02-16
Eddie Hung
abc9 to cope with non-wideports, count cells properly
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2019-02-16
Eddie Hung
Tidy up write_xaiger
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2019-02-16
Eddie Hung
write_aiger() to perform CI/CO post-processing and...
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2019-02-16
Eddie Hung
read_aiger() to cope with constant outputs, mixed widep...
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2019-02-15
Eddie Hung
Move lookup inside if
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2019-02-15
Eddie Hung
Fixes needed for DFF circuits
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2019-02-15
Eddie Hung
Refactor
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2019-02-15
Eddie Hung
Cope with width != 1 when re-mapping cells
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2019-02-15
Eddie Hung
abc9 to stitch results with CI/CO properly
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2019-02-15
Eddie Hung
read_aiger with more asserts, and call clean
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2019-02-15
Eddie Hung
write_xaiger to cope with unknown cells by transforming...
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2019-02-14
Eddie Hung
More cleanup
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2019-02-14
Eddie Hung
More cleanup of write_xaiger
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2019-02-14
Eddie Hung
Get rid of formal stuff from xaiger backend
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2019-02-14
Eddie Hung
synth_ice40 to have new -abc9 arg
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2019-02-14
Eddie Hung
Leave FIXME for clean
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2019-02-14
Eddie Hung
Use module->addLut()
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2019-02-14
Eddie Hung
Fix stitching
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2019-02-14
Eddie Hung
Use ConstEval to compute LUT masks
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2019-02-13
Eddie Hung
Merge remote-tracking branch 'origin/read_aiger' into...
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2019-02-13
Eddie Hung
Merge https://github.com/YosysHQ/yosys into xaig
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2019-02-13
Eddie Hung
Rip out some more stuff
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2019-02-13
Clifford Wolf
Fix sign handling of real constants
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2019-02-13
Eddie Hung
Rip out unused functions in abc9
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2019-02-12
Eddie Hung
Add support for read_aiger -wideports
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2019-02-12
Eddie Hung
Add support for read_aiger -map
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2019-02-12
Eddie Hung
Parse 'm' in xaiger
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2019-02-12
Eddie Hung
WIP for ABC with aiger
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2019-02-12
Eddie Hung
Missing headers for Xcode?
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2019-02-12
Eddie Hung
Merge branch 'read_aiger' of github.com:eddiehung/yosys...
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2019-02-12
Eddie Hung
Use module->add{Not,And}Gate() functions
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2019-02-12
Clifford Wolf
Merge pull request #802 from whitequark/write_verilog_a...
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2019-02-12
Clifford Wolf
Merge pull request #806 from daveshah1/fsm_opt_no_reset
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2019-02-11
Eddie Hung
Add read_xaiger
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2019-02-11
Eddie Hung
Add write_xaiger
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2019-02-11
Eddie Hung
Do not break for constraints
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2019-02-11
Eddie Hung
No increment line_count for binary ANDs
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2019-02-11
Eddie Hung
Do not ignore newline after AND in binary AIG
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2019-02-08
Eddie Hung
Copy backends/aiger/aiger.cc to xaiger.cc
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2019-02-08
Eddie Hung
Merge remote-tracking branch 'origin/dff_init' into...
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2019-02-08
Eddie Hung
Compile abc9
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2019-02-08
Eddie Hung
Refactor kernel/cost.h definition into cost.cc
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2019-02-08
Eddie Hung
Copy abc.cc to abc9.cc
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2019-02-08
Eddie Hung
addDff -> addDffGate as per @daveshah1
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2019-02-08
Eddie Hung
Fix tabulation
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2019-02-08
Eddie Hung
-module_name arg to go before -clk_name
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2019-02-08
Eddie Hung
Support and differentiate between ASCII and binary...
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2019-02-08
Eddie Hung
Add missing "[options]" to read_blif help
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2019-02-08
Eddie Hung
Allow module name to be determined by argument too
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2019-02-08
Eddie Hung
Refactor into AigerReader class
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2019-02-08
Eddie Hung
Parse binary AIG files
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2019-02-08
Eddie Hung
Add binary AIGs converted from AAG
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2019-02-08
Eddie Hung
Refactor to parse_aiger_header()
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2019-02-08
Eddie Hung
Add comment
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2019-02-08
Eddie Hung
Handle reset logic in latches
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2019-02-08
Eddie Hung
Change literal vars from int to unsigned
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2019-02-08
Eddie Hung
Create clk outside of latch loop
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2019-02-08
Eddie Hung
Handle latch symbols too
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2019-02-08
Eddie Hung
Remove return after log_error
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2019-02-08
Eddie Hung
Add support for symbol tables
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2019-02-08
Eddie Hung
Stub for binary AIGER
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2019-02-07
David Shah
fsm_opt: Fix runtime error for FSMs without a reset...
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2019-02-06
Eddie Hung
Cope WIDTH of ff/latch cells is default of zero
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2019-02-06
Eddie Hung
Refactor
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2019-02-06
Eddie Hung
Remove check for cell->name[0] == '$'
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2019-02-06
Eddie Hung
Merge branch 'dff_init' of https://github.com/eddiehung...
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2019-02-06
Eddie Hung
Revert most of autotest.sh; for non *.v use Yosys to...
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2019-02-06
Eddie Hung
Refactor
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2019-02-06
Eddie Hung
write_verilog to cope with init attr on q when -noexpr
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2019-02-06
Eddie Hung
Add INIT parameter to all ff/latch cells
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2019-02-06
Eddie Hung
Add tests for simple cases using defparam
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2019-02-06
Eddie Hung
Add -B option to autotest.sh to append to backend_opts
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2019-02-06
Eddie Hung
Extend testcase
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2019-02-06
Eddie Hung
Add testcase
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2019-02-06
Eddie Hung
Rename ASCII tests
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2019-02-06
Eddie Hung
WIP
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2019-02-06
Clifford Wolf
Add missing blackslash-to-slash convertion to smtio...
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2019-02-05
Eddie Hung
Add tests
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2019-01-29
whitequark
write_verilog: correctly emit asynchronous transparent...
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2019-01-27
Clifford Wolf
Merge pull request #798 from mmicko/master
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2019-01-27
Clifford Wolf
Merge pull request #800 from whitequark/write_verilog_t...
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2019-01-27
Clifford Wolf
Merge branch 'whitequark-write_verilog_keyword'
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2019-01-27
Clifford Wolf
Remove asicworld tests for (unsupported) switch-level...
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2019-01-27
whitequark
write_verilog: write $tribuf cell as ternary.
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2019-01-27
whitequark
write_verilog: escape names that match SystemVerilog...
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2019-01-25
David Shah
Merge pull request #796 from whitequark/proc_clean_typo
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2019-01-25
Miodrag Milanovic
Fixed Anlogic simulation model
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2019-01-23
whitequark
proc_clean: fix critical typo.
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2019-01-19
Clifford Wolf
Merge pull request #793 from whitequark/proc_clean_fix_...
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2019-01-18
whitequark
proc_clean: fix fully def check to consider compare...
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2019-01-17
Clifford Wolf
Cleanups in igloo2 example design
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2019-01-17
Clifford Wolf
Add SF2 IO buffer insertion
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2019-01-17
Clifford Wolf
Improve Igloo2 example
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2019-01-17
Clifford Wolf
Add "synth_sf2 -vlog", fix "synth_sf2 -edif"
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2019-01-17
Clifford Wolf
Add "write_edif -gndvccy"
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