yosys.git
2014-08-22 Clifford WolfAdded DPI-C documentation to README file
2014-08-22 Clifford WolfAdded support for non-standard <plugin>:<c_name> DPI...
2014-08-22 Clifford WolfArchibald Rust and Clifford Wolf: ffi-based dpi_call()
2014-08-22 Clifford WolfAdded "plugin" command
2014-08-22 Clifford WolfUpdated ABC to 4d547a5e065b
2014-08-21 Clifford WolfCosmetic changes to FSM tests
2014-08-21 Clifford WolfFixed small memory leak in ast simplify
2014-08-21 Clifford WolfAdded support for DPI function with different names...
2014-08-21 Clifford WolfAdded AstNode::asInt()
2014-08-21 Clifford WolfFixed memory leak in DPI function calls
2014-08-21 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-08-21 Clifford WolfAdded Verilog/AST support for DPI functions (dpi_call...
2014-08-21 Clifford WolfAdded support for global tasks and functions
2014-08-19 Clifford WolfAdded mod->addGate() methods for new gate types
2014-08-18 Clifford WolfUsing "via_celltype" in $mul carry-save-acc implementation
2014-08-18 Clifford WolfAdded "via_celltype" attribute on task/func
2014-08-17 Clifford WolfPerformance fix for new $__lcu techmap rule
2014-08-17 Clifford WolfReplaced recursive lcu scheme with bk adder
2014-08-17 Clifford WolfAdded const folding of AST_CASE to AST simplifier
2014-08-17 Clifford WolfFixed proc_{self,share}_dirname error handling
2014-08-17 Clifford WolfMakefile fixes
2014-08-17 Clifford WolfImproved AST ProcessGenerator performance
2014-08-17 Clifford WolfImproved sig.remove2() performance
2014-08-16 Clifford WolfUse stackmap<> in AST ProcessGenerator
2014-08-16 Clifford WolfAdded stackmap<> container
2014-08-16 Clifford WolfRenamed toposort.h to utils.h
2014-08-16 Clifford WolfAdded module->uniquify()
2014-08-16 Clifford WolfFixed AOI/OAI expr handling in verilog backend
2014-08-16 Clifford WolfMultiply using a carry-save accumulator
2014-08-16 Clifford WolfAdded "test_cell -s <seed>"
2014-08-16 Clifford WolfAST ProcessGenerator: replaced subst_*_{from,to} with...
2014-08-16 Clifford WolfAdded additional gate types: $_NAND_ $_NOR_ $_XNOR_...
2014-08-16 Clifford WolfAdded CellTypes::cell_evaluable()
2014-08-16 Clifford WolfChanges in techmap $__alu interface
2014-08-16 Clifford WolfAdded "opt -fast"
2014-08-16 Clifford WolfAdded log_spacer()
2014-08-15 Clifford WolfBugfix in iopadmap
2014-08-15 Clifford WolfRenamed $lut ports to follow A-Y naming scheme
2014-08-15 Clifford WolfRenamed $_INV_ cell type to $_NOT_
2014-08-15 Clifford WolfRemoved old doc references to $safe_pmux
2014-08-15 Clifford WolfMore idstring sort_by_* helpers and fixed tpl ordering...
2014-08-15 Clifford WolfAdded Frontend "+/" filename syntax for files from...
2014-08-15 Clifford Wolfdocument "techmap -map %<design-name>"
2014-08-14 Clifford WolfFixed bug in "read_verilog -ignore_redef"
2014-08-14 Clifford WolfAdded RTLIL::SigSpec::to_sigbit_map()
2014-08-14 Clifford WolfChanged the AST genWidthRTLIL subst interface to use...
2014-08-14 Clifford WolfAdded sig.{replace,remove,extract} variants for std...
2014-08-14 Clifford WolfFixed line numbers when using here-doc macros
2014-08-14 Clifford WolfFixed handling of task outputs
2014-08-14 Clifford WolfSimplified $__arraymul techmap rule
2014-08-14 Clifford WolfAdded module->ports
2014-08-14 Clifford WolfRefactoring of CellType class
2014-08-14 Clifford WolfRIP $safe_pmux
2014-08-14 Clifford WolfSome improvements in FSM mapping and recoding
2014-08-14 Clifford WolfAdded "abc -D" for setting delay target
2014-08-14 Clifford WolfUpdated ABC to 4935c2b946de
2014-08-13 Clifford WolfAdded techmap support for actual lookahead carry unit
2014-08-13 Clifford WolfPreparations for lookahead ALU support in techmap.v
2014-08-13 Clifford WolfFilter ANSI escape sequences from ABC output
2014-08-13 Clifford WolfNew interface for $__alu in techmap.v
2014-08-13 Clifford WolfAdded support for non-standard """ macro bodies
2014-08-12 Clifford WolfFixed handling of constant-true branches in proc_clean
2014-08-12 Clifford WolfAdded test_verific mode to tests/fsm/generate.py
2014-08-12 Clifford WolfFixed SigBit(RTLIL::Wire *wire) constructor
2014-08-12 Clifford WolfFixed building verific bindings
2014-08-12 Clifford WolfAdded multi-dim memory test (requires iverilog git...
2014-08-11 Clifford WolfAnother build fix by americanrouter (via reddit)
2014-08-10 Clifford WolfFixed FSM mapping for multiple reset-like signals
2014-08-09 Clifford WolfFixed "share" for complex scenarios with never-active...
2014-08-09 Clifford WolfDo not share any $reduce_* cells (its complicated and...
2014-08-09 Clifford WolfSome improvements in fsm_opt and fsm_map for FSM with...
2014-08-08 Clifford WolfImproved FSM tests
2014-08-08 Clifford WolfAnother fsm_extract bugfix
2014-08-08 Clifford WolfFixed "fsm -export"
2014-08-08 Clifford WolfFixed sharing of reduce operator
2014-08-08 Clifford WolfFixed fsm_extract for wreduced muxes
2014-08-08 Clifford WolfAdded FSM test bench
2014-08-08 Clifford WolfAdded "sat -prove-skip"
2014-08-07 Clifford WolfFixed build with gcc-4.6
2014-08-07 Clifford WolfUse "-keepdc" in "miter -equiv -flatten"
2014-08-07 Clifford WolfAlso allow "module foobar(input foo, output bar, ....
2014-08-07 Clifford WolfAdded adff2dff.v (for techmap -share_map)
2014-08-06 Clifford WolfAdded AST_MULTIRANGE (arrays with more than 1 dimension)
2014-08-06 Clifford WolfVarious improvements in memory_dff pass
2014-08-05 Clifford WolfVarious fixes and improvements in wreduce pass
2014-08-05 Clifford WolfRemoved old "constmap" from wreduce code
2014-08-05 Clifford WolfAdded support for truncating of wires to wreduce pass
2014-08-05 Clifford WolfCleanups and improvements in wreduce pass
2014-08-05 Clifford WolfAdded mux support to wreduce command
2014-08-05 Clifford WolfImproved scope resolution of local regs in Verilog...
2014-08-05 Clifford WolfFixed AST handling of variables declared inside a funct...
2014-08-04 Clifford WolfAdded "show -signed"
2014-08-04 Clifford WolfAdded support for non-standard "module mod_name(.....
2014-08-04 Clifford WolfAdded RTLIL::IdString::in(...)
2014-08-03 Clifford WolfFixed "share" for memory read ports
2014-08-03 Clifford WolfAdded "wreduce" to some of the standard test benches
2014-08-03 Clifford WolfProgress in "wreduce" pass
2014-08-03 Clifford WolfAdded "wreduce" command (work in progress)
2014-08-03 Clifford WolfAdded query() API to ModIndex
2014-08-03 Clifford WolfAdded ID() macro for static IdStrings
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