yosys.git
2017-01-01 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-01-01 Clifford WolfAdded cell port resizing to hierarchy pass
2017-01-01 Andrew Zonenberggreenpak4: Added POUT to GP_COUNTx cells
2016-12-31 Clifford WolfUpdated ABC to hg id 55cd83f432c0
2016-12-31 Clifford WolfBugfix in RTLIL::SigSpec::remove2()
2016-12-29 Clifford WolfUpdated ABC to hg id 8c6a635f7a20
2016-12-29 Clifford WolfImproved write_json help message
2016-12-26 Clifford WolfUpdated ABC to hg id f591c081d5e7
2016-12-24 Clifford WolfMerge pull request #284 from azonenberg/master
2016-12-23 Andrew ZonenbergMerge pull request #1 from azonenberg-hk/master
2016-12-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-23 Clifford WolfSimplified log_spacer() code
2016-12-22 Clifford WolfAdded "yosys -W regex"
2016-12-21 Clifford WolfAdded AIGER back-end to automatic back-end detection
2016-12-21 Clifford WolfUpdated ABC to hg rev a4872e22c646
2016-12-21 Clifford WolfUpdated ABC to hg rev 8bab2eedbba4
2016-12-21 Andrew Zonenberggreenpak4: Added INT pin to GP_SPI
2016-12-21 Andrew Zonenberggreenpak4: removed unused MISO pin from GP_SPI
2016-12-20 Andrew Zonenberggreenpak4: Removed SPI_BUFFER parameter
2016-12-20 Andrew Zonenberggreenpak4: replaced MOSI/MISO with single one-way SDAT pin
2016-12-20 Andrew Zonenberggreenpak4: Changed port names on GP_SPI for clarity
2016-12-20 Andrew Zonenberggreenpak4: Initial implementation of GP_SPI cell
2016-12-17 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-17 Andrew Zonenberggreenpak4: Updated GP_DCMP cell model
2016-12-16 Andrew Zonenberggreenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.
2016-12-15 Clifford WolfAdded "verilog_defines" command
2016-12-15 Andrew Zonenberggreenpak4: Initial version of GP_DCMP skeleton (not...
2016-12-14 Andrew Zonenberggreenpak4: More fixups of GP_DCMPx cells
2016-12-14 Andrew Zonenberggreenpak4: And another typo :(
2016-12-14 Andrew Zonenberggreenpak4: Fixed another typo
2016-12-14 Andrew Zonenberggreenpak4: Fixed typo
2016-12-14 Andrew Zonenberggreenpak4: Cleaned up trailing spaces in cells_sim
2016-12-14 Andrew Zonenberggreenpak4: Added GP_DCMPREF / GP_DCMPMUX
2016-12-13 Clifford WolfBugfix in comment handling
2016-12-12 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-11 Clifford WolfAdded $anyconst support to AIGER back-end
2016-12-11 Clifford WolfMerge branch 'LSS-USP-unit-test-structure'
2016-12-11 Clifford WolfSome minor CodingReadme changes in unit test section
2016-12-11 Clifford WolfBuild hotfix in tests/unit/Makefile
2016-12-11 Andrew ZonenbergAdded GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF
2016-12-10 rodrigosiqueiraImproved unit test structure
2016-12-10 Andrew Zonenberggreenpak4: Added support for inferred input/output...
2016-12-10 Andrew Zonenberggreenpak4: Can now techmap inferred D latches (without...
2016-12-10 Andrew Zonenberggreenpak4: Inverted D latch cells now have nQ instead...
2016-12-06 Andrew ZonenbergAdded GP_DLATCH and GP_DLATCHI
2016-12-06 Andrew ZonenbergInitial implementation of techlib support for GreenPAK...
2016-12-06 Andrew ZonenbergUpdated help text for synth_greenpak4
2016-12-04 rodrigosiqueiraAdded explanation about configure and create test
2016-12-04 rodrigosiqueiraAdded required structure to implement unit tests
2016-12-03 Clifford WolfAdded $assert/$assume support to AIGER back-end
2016-12-03 Clifford WolfImproved yosys-smtbmc default -t/--assume-skipped for...
2016-12-01 Clifford WolfUpdated ABV to hg rev 8b555d9e67cf
2016-12-01 Clifford WolfAdded examples/aiger/
2016-12-01 Clifford WolfAdded "yosys-smtbmc --aig"
2016-12-01 Clifford WolfAdded support for partially initialized regs to smt2...
2016-12-01 Clifford WolfAdded "write_aiger -zinit -symbols -vmap"
2016-11-30 Clifford WolfAdded "write_aiger" command
2016-11-30 Clifford WolfAdded "design -reset-vlog"
2016-11-29 Clifford WolfImproved equiv_purge log output
2016-11-28 Clifford WolfBugfix in smt2 back-end for pure checker modules
2016-11-28 Clifford WolfAdded support for macros as include file names
2016-11-28 Clifford WolfBugfix in "read_verilog -D NAME=VAL" handling
2016-11-27 Clifford WolfRemoved shebang line from smtio.py, fixes #279
2016-11-23 Clifford WolfAdded wire start_offset and upto handling BLIF back-end
2016-11-23 Clifford WolfAdded wire start_offset and upto handling to splitnets cmd
2016-11-22 Clifford WolfMerge pull request #274 from oldtopman/lcurses
2016-11-22 Clifford WolfAdded "yosys-smtbmc --append"
2016-11-22 oldtopmanAdded optional flag for linking curses with readline.
2016-11-19 Clifford WolfMerge pull request #272 from AlexDaniel/master
2016-11-19 Aleks-Daniel... Keep lines under 80 characters
2016-11-19 Clifford WolfImproved ABC default scripts
2016-11-19 Aleks-Daniel... Markdownify README even further
2016-11-19 Clifford WolfMerge pull request #271 from azidar/bugfix-assign-wmask
2016-11-18 Adam IzraelevitzBugfix: include assign to write-mask
2016-11-18 Clifford WolfMore progress in FIRRTL back-end
2016-11-17 Clifford WolfProgress in FIRRTL back-end
2016-11-17 Clifford WolfAdded first draft of FIRRTL back-end
2016-11-16 Clifford WolfCleanups and fixed in write_verilog regarding reg init
2016-11-15 Clifford WolfAdded support for hierarchical defparams
2016-11-15 Clifford WolfRemember global declarations and defines accross read_v...
2016-11-13 Clifford WolfMerge pull request #268 from AlexDaniel/master
2016-11-12 Aleks-Daniel... Markdownify README
2016-11-09 Clifford WolfMinor bugfix in submod
2016-11-08 Clifford WolfProgress in examples/gowin/
2016-11-08 Clifford WolfIndenting fixes in gowin sim cell lib
2016-11-08 Clifford WolfBugfix in "setundef" pass
2016-11-07 Clifford WolfAdded examples/gowin/
2016-11-05 Clifford WolfImplemented "scc -set_attr"
2016-11-05 Clifford WolfBugfix in "scc" command
2016-11-04 Clifford WolfFixed anonymous genblock object names
2016-11-03 Clifford WolfAdded hex constant support to write_verilog
2016-11-03 Clifford WolfWe are now in 0.7+ development
2016-11-03 Clifford WolfYosys 0.7 yosys-0.7
2016-11-02 Clifford WolfBugfix in "hierarchy -check"
2016-11-02 Clifford WolfUpdated command reference in manual
2016-11-02 Clifford WolfChangelog for Yosys 0.7
2016-11-02 Clifford WolfAdded support for fsm_encoding="user"
2016-11-02 Clifford WolfAdded "fsm_expand -full"
2016-11-01 Clifford WolfSome fixes in handling of signed arrays
2016-11-01 Clifford WolfiCE40 flow is not experimental anymore
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