openpower-isa.git
2021-12-09 Jacob Lifshayrename ternaryi to ternlogi
2021-12-09 Jacob Lifshayadd initial ternlogi pseudo-code
2021-12-08 Luke Kenneth... add instr_fault to PowerDecoder2
2021-12-08 Luke Kenneth... whitespace
2021-12-08 Luke Kenneth... code-comments for LDSTException.instr_fault
2021-12-08 Luke Kenneth... add an on_Display function which is being used by some...
2021-12-08 Luke Kenneth... found a way to print out the names of the signals
2021-12-08 Luke Kenneth... absolute import again
2021-12-08 Luke Kenneth... use full-path imports (so we know where they come from)
2021-12-08 Mikolaj WielgusWIP: Output C instead of Python for Nmigen simulation
2021-12-08 Mikolaj WielgusSource Nmigen simulator from this repository
2021-12-07 Luke Kenneth... whoops wrong number
2021-12-07 Luke Kenneth... add OP_FETCH_FAILED micro-op
2021-12-07 Jacob Lifshayfix broken url
2021-12-05 Tobias Platenfix microwatt_mmu and and wishbone_memory output in...
2021-12-05 Luke Kenneth... connect to dcache.bus standard interface when using...
2021-12-05 Luke Kenneth... correct import of wb_get function
2021-12-04 Luke Kenneth... add name parameter to wb_get
2021-12-04 Luke Kenneth... add wb_get function for emulating wishbone interface
2021-12-04 Luke Kenneth... raise a MemException in ISACaller RADIXMMU
2021-12-04 Luke Kenneth... enable MMU in SimRunner if requested. now HDL and...
2021-12-04 Luke Kenneth... test in SimState for access to RADIX memory, bypass...
2021-12-03 Luke Kenneth... add a namedtuple LDSTExceptionTuple which allows obtaining
2021-12-03 Luke Kenneth... add link to exceptions in gtkw traces
2021-12-02 Luke Kenneth... regspec_decode_write now stores the decoded write info...
2021-12-02 Luke Kenneth... specify length in RegDecodeInfo explicitly so that...
2021-12-02 Luke Kenneth... use namedtuple in get_rdflags
2021-12-02 Luke Kenneth... use namedtuple for regspec_decode
2021-12-02 Luke Kenneth... add module to regspec_decode_* and get_rdflags
2021-12-02 Jacob Lifshaymove ternlogi to SHIFT_ROT unit
2021-12-02 Jacob Lifshayfix sv_analysis command, cuz script created by setup...
2021-12-02 Jacob Lifshayformat code
2021-12-01 Luke Kenneth... fix expected state in hazard test
2021-12-01 Luke Kenneth... fix expected state in hazard case_regression_1
2021-12-01 Luke Kenneth... add a proper twin addi regression which tests Reservati...
2021-12-01 Luke Kenneth... add regspec_decode which takes readmode arg and returns...
2021-11-30 Dmitry Selyutinsv_analysis: decouple declarations and definitions
2021-11-30 Dmitry Selyutinsv_analysis: use is instead of eq for enums
2021-11-30 Dmitry Selyutinsv_analysis: fix single-line binutils comments
2021-11-30 Luke Kenneth... add randomised hazard test
2021-11-30 Luke Kenneth... add two more hazard tests
2021-11-30 Luke Kenneth... attempting to use PowerDecode2 in non-svp64 mode
2021-11-27 Dmitry Selyutinsv_analysis: decouple common disclaimer
2021-11-27 Dmitry Selyutinsv_analysis: introduce stub binutils format
2021-11-27 Dmitry Selyutinsv_analysis: support format argument
2021-11-27 Luke Kenneth... add extra overlap hazard test
2021-11-26 R Veera KumarShorten expected state code for case_extsb using exts...
2021-11-26 R Veera KumarShorten expected state code for case_extsb in alu_cases...
2021-11-26 R Veera KumarShorten expected state code for case_rand in alu_cases...
2021-11-26 R Veera KumarShorten case_rand_imm alu test case code
2021-11-26 R Veera KumarMake carry_out32 variable boolean and expected state...
2021-11-25 R Veera KumarShortened code in case_addis_nonzero_r0 alu test case
2021-11-25 R Veera KumarCorrect add-equal operator in case_rand_imm
2021-11-25 R Veera KumarShort the code of case_rand_imm
2021-11-24 R Veera KumarFix line so that 80 characters per line is kept and...
2021-11-24 R Veera KumarAdd expected state to case_rand_imm in alu_cases unit...
2021-11-24 Luke Kenneth... corrections to hazard overlap test
2021-11-24 Luke Kenneth... add extra hazard unit tests
2021-11-24 Luke Kenneth... tidyup on case_0_adde
2021-11-24 Luke Kenneth... correct write-after-write hazard test (expected values)
2021-11-23 R Veera KumarAdd expected state to case_0_adde in alu_cases unit...
2021-11-23 Luke Kenneth... add write-after-write hazard test for inorder core
2021-11-23 R Veera KumarAdd expected state to case_rand in alu_cases unit test
2021-11-23 R Veera KumarAdd expected state to case_addis_nonzero_r0 in alu_case...
2021-11-23 R Veera KumarAdd expected state to case_extsb in alu_cases unit...
2021-11-23 R Veera KumarAdd computed CR0 to expected version of case_adde_0
2021-11-22 Luke Kenneth... add expected version of case_adde_0
2021-11-22 Luke Kenneth... adding a couple more hazard avoidance cases
2021-11-22 R Veera KumarAdd expected state to case_cmpeqb in alu_cases unit...
2021-11-22 R Veera KumarAdd expected state to case_cmplw_microwatt_1 in alu_cas...
2021-11-22 R Veera KumarAdd expected state to case_cmpli_microwatt in alu_cases...
2021-11-22 R Veera KumarAdd expected state to case_cmpl_microwatt_0_disasm...
2021-11-22 R Veera KumarAdd expected state to case_cmpl_microwatt_0 in alu_case...
2021-11-22 R Veera KumarAdd expected state to case_addme_ca_so_4 in alu_cases...
2021-11-22 R Veera KumarAdd expected state to case_addme_ca_so_3 in alu_cases...
2021-11-22 R Veera KumarAdd expected state to case_addme_ca_1 in alu_cases...
2021-11-21 Luke Kenneth... sigh, for overlap mode there is no safe way to get...
2021-11-21 Luke Kenneth... move dump state to base class State in test API
2021-11-21 R Veera KumarAdd expected state to case_cmp3 in alu_cases unit test
2021-11-21 R Veera KumarAdd expected state to case_cmp2 in alu_cases unit test
2021-11-21 R Veera KumarAdd expected state to case_cmp in alu_cases unit test
2021-11-21 R Veera KumarAdd expected state to all of case_addze in alu_cases...
2021-11-17 Jacob Lifshayadd bitmanip_cases.py
2021-11-17 Jacob Lifshayrename ternary->ternlog and associated form/field TI...
2021-11-17 Luke Kenneth... add allow_overlap argument to TestRunnerBase
2021-11-17 Luke Kenneth... code-comments
2021-11-17 Luke Kenneth... XER regspec_decode_write was not sophisticated enough.
2021-11-17 Luke Kenneth... split up regression cases so that a single Rc=1 add...
2021-11-16 Luke Kenneth... truncate CR regspec_decode_write reg mask to 8 bit
2021-11-16 Luke Kenneth... argh, regspec_decode_write is supposed to return single...
2021-11-16 Luke Kenneth... name of cr reg3 was numbered 2
2021-11-13 Jacob Lifshayremove excess I from ternary-related names
2021-11-12 Jacob Lifshaychange ternaryi to correct register fields
2021-11-12 Jacob Lifshayformat code
2021-11-12 Jacob Lifshayformat code
2021-11-11 Luke Kenneth... add case-based expected results in addme alu_cases
2021-11-11 Luke Kenneth... invert speedup (commenting-out) of tests
2021-11-11 Luke Kenneth... sort out numbering on CRs in SimState
2021-11-11 Luke Kenneth... whitespace
2021-11-11 Luke Kenneth... fix test API State.compare which was overwriting intreg...
next