yosys.git
2013-11-06 Clifford WolfAdditional fixes for undef propagation in concat and...
2013-11-06 Clifford WolfImproved width extension with regard to undef propagation
2013-11-06 Clifford WolfFixed handling of undef values in POS cells in ConstEval
2013-11-06 Clifford WolfFixed handling of undef values in MUX select input...
2013-11-06 Clifford WolfAdded correct RTL undef handling to eval vloghammer...
2013-11-06 Clifford WolfAdded eval -vloghammer_report mode
2013-11-05 Clifford WolfAdded support for "keep" attributes on wires
2013-11-05 Clifford WolfFixed sign handling in const eval of sshl and sshr
2013-11-04 Clifford WolfMakefile DESTDIR default (/usr/local) without quotes
2013-11-04 Clifford WolfAnother fix for early width and sign detection in ast...
2013-11-04 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-11-04 Clifford WolfFixed const folding of ternary operator
2013-11-04 Clifford WolfUse proper bit width ans sign extension for const folding
2013-11-04 Clifford WolfMerge pull request #16 from mschmoelzer/master
2013-11-04 Martin SchmölzerAllow setting of installation destination via DESTDIR...
2013-11-04 Clifford WolfImproved comments on topological sort in edif backend
2013-11-04 Clifford WolfFixes for early width and sign detection in ast simplifier
2013-11-04 Clifford Wolffurther improved early width and sign detection in...
2013-11-03 Clifford WolfAdded simple topological sort to edif backend
2013-11-03 Clifford WolfWrite yosys version to output files
2013-11-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-11-03 Clifford WolfFixed detectSignWidthWorker (ast frontend) for AST_CONCAT
2013-11-03 Clifford WolfAdded resolution of positional arguments to hierarchy...
2013-11-03 Clifford WolfIgnore explicit unconnected ports in intersynth backend
2013-11-02 Clifford WolfBehavior should be identical now to rev. 0b4a64ac6adbd6...
2013-11-02 Clifford WolfAdded roadmap to readme file
2013-11-02 Clifford WolfVarious ast changes for early expression width detectio...
2013-10-31 Clifford WolfAdded DFFSR cell to techlibs/cmos/cmos_cells.lib
2013-10-31 Clifford WolfAdded placeholder check to dfflibmap and cleaned up...
2013-10-31 Clifford WolfChanged MiniSAT feater defines again
2013-10-31 Clifford WolfAdded paragraph to README file to avoid mycells.lib...
2013-10-31 Clifford WolfREADME file typo fix
2013-10-31 Clifford WolfSome additions to the README file
2013-10-30 Clifford WolfFixed ezminisat C++ errors: undef PRIi64
2013-10-29 Clifford WolfAdded detection for endless recursion in fsm_detect...
2013-10-29 Clifford WolfFixed help message typo (memory pass)
2013-10-29 Clifford WolfAdded -format option to splitnets
2013-10-27 Clifford WolfMerge pull request #12 from jameswalmsley/master
2013-10-27 James Walmsley[EXAMPLES] Ported the mojo counter example to Zynq...
2013-10-27 Clifford WolfFixed get_share_file_name() for installed yosys
2013-10-27 Clifford WolfCleanups in xilinx examples
2013-10-27 Clifford WolfAdded synth_xilinx command
2013-10-27 Clifford WolfAdded API and Makefile rules for share/ files
2013-10-27 Clifford WolfAdded design->full_selection() helper method
2013-10-27 Clifford WolfMoved simple xilinx counter sim example to subdir
2013-10-27 Clifford WolfXilinx mojo_counter example is now working
2013-10-27 Clifford WolfFixed hex string generation bug in edif backend
2013-10-26 Clifford WolfRenamed techlibs/xilinx7 to techlibs/xilinx
2013-10-26 Clifford WolfImproved xilinx mojo_counter example
2013-10-26 Clifford WolfAdded support for i/o buffers to iopadmap
2013-10-26 Clifford WolfAdded another xilinx example (not funcional yet)
2013-10-24 Clifford WolfAdded support for sr flip-flops to dfflibmap
2013-10-24 Clifford WolfAdded support for complex set-reset flip-flops in proc_dff
2013-10-24 Clifford WolfFixed handling of boolean attributes (passes)
2013-10-24 Clifford WolfFixed handling of boolean attributes (backends)
2013-10-24 Clifford WolfFixed handling of boolean attributes (frontends)
2013-10-24 Clifford WolfFixed handling of boolean attributes (kernel)
2013-10-23 Clifford WolfFixed parsing of value-less attributes in ilang
2013-10-21 Clifford WolfImproved handling of dff with async resets
2013-10-18 Clifford WolfAdded handling of multiple async paths in proc_arst
2013-10-18 Clifford WolfChanged NEW_WIRE API to return the wire, not the signal
2013-10-18 Clifford WolfAdded dffsr support to proc_dff pass
2013-10-18 Clifford WolfAdded RTLIL NEW_WIRE macro
2013-10-18 Clifford WolfBugfix in dffsr techmap rules
2013-10-18 Clifford WolfAdded techmap rules for $sr, $dffsr and $dlatch
2013-10-18 Clifford WolfAdded $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_...
2013-10-18 Clifford WolfAdded $sr, $dffsr and $dlatch cell types
2013-10-17 Clifford WolfImproved way of connecting ports in techmap pass
2013-10-17 Clifford WolfOnly prefer connected signals iff they have public...
2013-10-17 Clifford WolfAdded -buf, -true and -false options to blif backend
2013-10-17 Clifford WolfFixed bug in synthesis of memories that are never written
2013-10-17 Clifford WolfAvoid re-arranging signals on register outputs
2013-10-17 Clifford WolfFixed detection of major wires in opt_clean
2013-10-16 Clifford WolfAdded iopadmap pass
2013-10-16 Clifford WolfMoved dfflibmap from passes/dfflibmap to passes/techmap
2013-10-16 Clifford WolfAdded map, par and bitgen to xlinx7 example
2013-10-16 Clifford WolfFixed parsing or liberty file statements such as 'clock...
2013-10-11 Clifford WolfAdded recommended apt-get commands to README
2013-10-11 Clifford WolfFixed minisat include
2013-10-03 Clifford WolfPinned ABC revision to 0f9e5488ced3
2013-09-17 Clifford WolfImprovements in EDIF backend
2013-09-15 Clifford WolfAdded additional options to BLIF backend
2013-09-15 Clifford WolfAdded BLIF backend
2013-09-15 Clifford WolfA couple of small fixes in SPICE backend
2013-09-15 Clifford WolfMoved common techlib files to techlibs/common
2013-09-15 Clifford WolfUpdated manual
2013-09-14 Clifford WolfAdded spice testbench to techlibs/cmos
2013-09-14 Clifford WolfAdded spice backend
2013-09-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-09-03 Clifford WolfAdded -selected option to various backends
2013-08-28 Clifford WolfEncode large (>32 bits) parameters as hex string in...
2013-08-27 Clifford WolfImproved edif backend
2013-08-27 Clifford WolfAdded mapping to techlibs/xilinx7 testbench (exposes...
2013-08-22 Clifford WolfAdded simple xilinx7 technology mapping files
2013-08-22 Clifford WolfMore explicit integer output in verilog backend
2013-08-22 Clifford WolfAdded correct encoding of identifiers in EDIF backend
2013-08-22 Clifford WolfAdded edif backend (still under construction)
2013-08-21 Clifford WolfMerge pull request #10 from hansiglaser/master
2013-08-21 Clifford WolfSome minor documentation fixes
2013-08-21 Johann Glaserfixed Verilog parser filename and line numbering issue...
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