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litex.git
2012-03-30
Sebastien Bourdeauducq
sim: proxy
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2012-03-23
Sebastien Bourdeauducq
Update copyright notices
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2012-03-18
Sebastien Bourdeauducq
corelogic/fsm: typo
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2012-03-17
Sebastien Bourdeauducq
corelogic/fsm: delayed enters
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2012-03-16
Sebastien Bourdeauducq
corelogic/roundrobin: CE switching
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2012-03-15
Sebastien Bourdeauducq
corelogic: convert timeline to function and move to...
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2012-03-14
Sebastien Bourdeauducq
bus/asmibus/hub: require finalization before get_slots
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2012-03-14
Sebastien Bourdeauducq
fhdl: export log2_int
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2012-03-10
Alain Péteut
setup.py: simplify
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2012-03-10
Sebastien Bourdeauducq
doc: more examples and comments
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2012-03-10
Sebastien Bourdeauducq
doc: cosmetic changes (thanks sh4rm4 for reporting...
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2012-03-09
Sebastien Bourdeauducq
doc: use script font
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2012-03-09
Sebastien Bourdeauducq
doc: simulation
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2012-03-09
Sebastien Bourdeauducq
doc: cosmetic changes (thanks rofl0r for reporting...
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2012-03-09
Sebastien Bourdeauducq
doc: add logo
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2012-03-09
Sebastien Bourdeauducq
doc: switch to sphinx
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2012-03-08
Sebastien Bourdeauducq
examples: FIR filter simulation
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2012-03-08
Sebastien Bourdeauducq
fhdl: handle negative constants correctly
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2012-03-08
Sebastien Bourdeauducq
examples: remove outdated wb_intercon simulation
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2012-03-08
Sebastien Bourdeauducq
vpi: support extra include directories
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2012-03-08
Sebastien Bourdeauducq
gitignore: update
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2012-03-08
Sebastien Bourdeauducq
bus: generic transaction model
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2012-03-08
Sebastien Bourdeauducq
vpi: patch for Icarus Verilog
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2012-03-08
Sebastien Bourdeauducq
examples: small cleanup
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2012-03-08
Sebastien Bourdeauducq
sim: fix zero encoding
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2012-03-08
Sebastien Bourdeauducq
sim: fix message debug formatting
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2012-03-06
Sebastien Bourdeauducq
sim: make initialization cycle optional (selectable...
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2012-03-06
Sebastien Bourdeauducq
sim: memory access
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2012-03-06
Sebastien Bourdeauducq
fhdl: register memory objects with namespace
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2012-03-06
Sebastien Bourdeauducq
sim: support for signed numbers
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2012-03-06
Sebastien Bourdeauducq
fhdl/verilog: fix signed constant conversion
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2012-03-06
Sebastien Bourdeauducq
vpi: install target
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2012-03-06
Sebastien Bourdeauducq
sim: VCD generation
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2012-03-06
Sebastien Bourdeauducq
sim: clean startup/shutdown
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2012-03-06
Sebastien Bourdeauducq
sim: remove temporary files and socket
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2012-03-06
Sebastien Bourdeauducq
fhdl/namer: do not reference objects with __del__ metho...
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2012-03-06
Sebastien Bourdeauducq
sim: remove default sockaddr
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2012-03-06
Sebastien Bourdeauducq
fhdl: add simulation functions in fragment
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2012-03-05
Sebastien Bourdeauducq
sim: basic functionality working
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2012-03-05
Sebastien Bourdeauducq
sim: signal writes working
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2012-03-04
Sebastien Bourdeauducq
sim: cleanups
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2012-03-04
Sebastien Bourdeauducq
sim: signal reads working
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2012-03-04
Sebastien Bourdeauducq
sim: compile VPI module
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2012-03-04
Sebastien Bourdeauducq
sim: two way IPC working
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2012-03-03
Sebastien Bourdeauducq
sim: IPC module (lacks str/int encoding)
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2012-02-29
Sebastien Bourdeauducq
README: clarify license
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2012-02-19
Sebastien Bourdeauducq
bus/dfi: fix multiphase naming
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2012-02-18
Sebastien Bourdeauducq
bank/csrgen: fix RE generation
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2012-02-17
Sebastien Bourdeauducq
bank: add RE signal for registers made of fields
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2012-02-17
Sebastien Bourdeauducq
bus: add interconnect statements function
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2012-02-17
Sebastien Bourdeauducq
fhdl: check we pass BV to signals
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2012-02-17
Sebastien Bourdeauducq
fhdl/verilog: properly connect instance inouts
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2012-02-16
Sebastien Bourdeauducq
fhdl: support forwarding of bidirectional signals from...
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2012-02-15
Sebastien Bourdeauducq
bus/dfi: filter signals by direction
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2012-02-15
Sebastien Bourdeauducq
bank: omit device write register when access_bus==READ_...
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2012-02-15
Sebastien Bourdeauducq
bus: add DFI
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2012-02-15
Sebastien Bourdeauducq
bank/csrgen: use new bus API
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2012-02-15
Sebastien Bourdeauducq
bus: fix simple interconnect
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2012-02-15
Sebastien Bourdeauducq
bus: simplify and cleanup
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2012-02-14
Sebastien Bourdeauducq
bus/asmibus/hub: forward data and tag_call
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2012-02-14
Sebastien Bourdeauducq
Use double quotes for all strings
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2012-02-13
Sebastien Bourdeauducq
bus/wishbone2asmi: cache hits working
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2012-02-13
Sebastien Bourdeauducq
corelogic: support reverse in displacer/chooser
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2012-02-13
Sebastien Bourdeauducq
Fix syntax errors and other stupid problems
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2012-02-13
Sebastien Bourdeauducq
bus/csr: Rename a->adr d->dat to be consistent with...
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2012-02-13
Sebastien Bourdeauducq
doc: update ASMI description
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2012-02-13
Sebastien Bourdeauducq
bus/wishbone2asmi: set WM, and send 0 when inactive
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2012-02-13
Sebastien Bourdeauducq
bus: Wishbone to ASMI caching bridge (untested)
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2012-02-11
Sebastien Bourdeauducq
corelogic/misc: displacer + chooser
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2012-02-11
Sebastien Bourdeauducq
corelogic/misc/multimux: less confusing variable name
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2012-02-11
Sebastien Bourdeauducq
bus/asmibus: fix typo
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2012-02-11
Sebastien Bourdeauducq
corelogic/record: add to_signal convenience function
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2012-02-11
Sebastien Bourdeauducq
corelogic/misc: contiguous split
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2012-02-10
Sebastien Bourdeauducq
bus/asmibus: add get_slots, fix get_fragment
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2012-02-10
Sebastien Bourdeauducq
bus: ASMI hub (untested)
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2012-02-08
Sebastien Bourdeauducq
doc: update Bank description
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2012-02-06
Sebastien Bourdeauducq
bus/wishbone2csr: truncate WB data
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2012-02-06
Sebastien Bourdeauducq
fhdl: do not attempt slicing non-array signals to keep...
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2012-02-06
Sebastien Bourdeauducq
bank: event manager
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2012-02-06
Sebastien Bourdeauducq
bank: support registers larger than the bus word width
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2012-02-06
Sebastien Bourdeauducq
bank: refactoring
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2012-02-06
Sebastien Bourdeauducq
bank/csrgen: use enumerate
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2012-02-05
Sebastien Bourdeauducq
fhdl/structure: binary constant builder
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2012-02-03
Sébastien Bourdeauducq
Merge pull request #2 from larsclausen/master
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2012-02-02
Lars-Peter...
Use enumerate(x) instead of zip(range(x), x)
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2012-02-02
Lars-Peter...
fhdl/namer: Add support for STORE_DEREF opcode
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2012-02-02
Lars-Peter...
Lower required python version to 3.1
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2012-01-28
Sebastien Bourdeauducq
examples/wb_intercon: update to new APIs
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2012-01-28
Sebastien Bourdeauducq
fhdl/namer: extract variable names with bytecode inspection
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2012-01-28
Sebastien Bourdeauducq
fhdl: do not prefix instance signal names
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2012-01-27
Sebastien Bourdeauducq
Remove explicit bus names and rely on the new automatic...
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2012-01-27
Sebastien Bourdeauducq
fhdl: support memory read enable
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2012-01-27
Sebastien Bourdeauducq
fhdl: make WRITE_FIRST default
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2012-01-27
Sebastien Bourdeauducq
doc: memories
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2012-01-27
Sebastien Bourdeauducq
fhdl: memories working
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2012-01-27
Sebastien Bourdeauducq
fhdl/verilog: clean up signal classification and suppor...
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2012-01-27
Sebastien Bourdeauducq
fhdl/structure: memory description
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2012-01-27
Sebastien Bourdeauducq
doc: cosmetic changes
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2012-01-26
Sebastien Bourdeauducq
doc: ASMI description
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2012-01-25
Sebastien Bourdeauducq
Remove duplicate logo
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