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gem5.git
2019-05-02 Giacomo Travaglinidev-arm: GICv3 LPI tables are using physical addresses commit | commitdiff | tree
2019-05-02 Giacomo Travaglinidev-arm: Fix GICv3 LPI loop commit | commitdiff | tree
2019-05-02 Giacomo Travaglinidev-arm: Fix Bitwise operation in GICv3 commit | commitdiff | tree
2019-05-02 Daniel R. Carvalhotests: Add missing kernels to system creation commit | commitdiff | tree
2019-04-30 Gabe Blackarch: Stop using TheISA within the ISAs. commit | commitdiff | tree
2019-04-30 Gabe Blackx86: Get rid of some unnecessary TheISA-es in x86. commit | commitdiff | tree
2019-04-30 Gabe Blacksparc: Move translation constants from isa_traits.hh... commit | commitdiff | tree
2019-04-30 Gabe Blacksparc: Move the interrupt types out of isa_traits.hh... commit | commitdiff | tree
2019-04-30 Gabe Blackarch: Remove the mt.hh switching header. commit | commitdiff | tree
2019-04-30 Gabe Blackcpu: alpha: Delete all occurrances of the simPalCheck... commit | commitdiff | tree
2019-04-30 Gabe Blackalpha: Implement simPalCheck within the ISA description. commit | commitdiff | tree
2019-04-30 Gabe Blackcpu: Remove hwrei from the generic interfaces. commit | commitdiff | tree
2019-04-30 Alexandru Dutusim-se: use DPRINTF_SYSCALL for ioctl/wait4 commit | commitdiff | tree
2019-04-30 Brandon Pottersim-se: bugfix for 54c77aa055e commit | commitdiff | tree
2019-04-30 Gabe Blackarch: cpu: Track kernel stats using the base ISA agnost... commit | commitdiff | tree
2019-04-30 Gabe Blackalpha: Implement HWREI in the ISA. commit | commitdiff | tree
2019-04-30 Gabe Blackalpha: Add some control registers to the ISA operands... commit | commitdiff | tree
2019-04-30 Brandon Pottersim-se: add socket ioctls commit | commitdiff | tree
2019-04-30 Gabe Blacksystemc: Add a distinct async_request_update mechanism. commit | commitdiff | tree
2019-04-29 Gabe Blackcpu: Get rid of the (read|set)RegOtherThread methods. commit | commitdiff | tree
2019-04-29 Gabe Blackmips: Implement readRegOtherThread and setRegOtherThrea... commit | commitdiff | tree
2019-04-29 Gabe Blackcpu: Include debug flags regardless of whether the... commit | commitdiff | tree
2019-04-29 Steve Reinhardtsim-se: create Proc out files in out dir commit | commitdiff | tree
2019-04-29 Giacomo Travagliniarch-arm: Faults DebugFlag now printing inst opcode... commit | commitdiff | tree
2019-04-29 Giacomo Travagliniarch-arm: Report real instruction encoding when Undefined commit | commitdiff | tree
2019-04-28 Gabe Blackarch, sim: Simplify the AuxVector type. commit | commitdiff | tree
2019-04-28 Gabe Blackmem: Remove the ISA specialized versions of port proxy... commit | commitdiff | tree
2019-04-28 Gabe Blackmem: Minimize the use of MemObject. commit | commitdiff | tree
2019-04-27 Gabe Blackpython: Get rid of the VectorPort constructor. commit | commitdiff | tree
2019-04-27 Gabe Blackpython: Replace the Master/Slave Ports with Request... commit | commitdiff | tree
2019-04-26 Giacomo Travagliniarch-arm: updateMiscReg not setting isHyp in aarch64 commit | commitdiff | tree
2019-04-26 Gabe Blackarm: Factor some repetition out of the ProcessInfo... commit | commitdiff | tree
2019-04-25 Gabe Blackarm: Fix some style issues in stacktrace.cc. commit | commitdiff | tree
2019-04-25 Gabe Blackx86: Refactor the ProcessInfo constructor. commit | commitdiff | tree
2019-04-25 David Hasheconfigs: faux-filesystem fix w/ ruby in se mode commit | commitdiff | tree
2019-04-25 Gabe Blackx86: Fix some style issues in stacktrace.cc. commit | commitdiff | tree
2019-04-25 David Hashesim-se: add a faux-filesystem commit | commitdiff | tree
2019-04-25 Giacomo Travagliniarch-arm: Remove un-needed hyp flag in TLBI operations commit | commitdiff | tree
2019-04-25 Giacomo Travagliniarch-arm: Correct target EL field in TLBI operations commit | commitdiff | tree
2019-04-25 Giacomo Travaglinidev-arm: Move GICv3 (Re)Ditributor address in Realview.py commit | commitdiff | tree
2019-04-25 Giacomo Travaglinidev-arm: Limit number of max PE in GICv3 to 128 commit | commitdiff | tree
2019-04-25 Giacomo Travaglinidev-arm: Add GICv4 extension switch in GICv3 commit | commitdiff | tree
2019-04-25 Giacomo Travaglinidev-arm: Check for maximum number of supported PE in... commit | commitdiff | tree
2019-04-24 Javier Buenoconfig: Add flag options to set the hardware prefetcher... commit | commitdiff | tree
2019-04-24 Andrea Mondellicpu,mem: missing override specifier commit | commitdiff | tree
2019-04-24 Gabe Blacksystemc: Use the new TLM socket types in the TLM bridge... commit | commitdiff | tree
2019-04-24 Gabe Blacksystemc: Add Port types for initiator and target sockets. commit | commitdiff | tree
2019-04-24 Gabe Blackdev: Use the new Port role mechanism to make an EtherIn... commit | commitdiff | tree
2019-04-24 Gabe Blackpython: Generalize the Port.splice function. commit | commitdiff | tree
2019-04-24 Gabe Blackpython: Generalize the dot_writer to handle non Master... commit | commitdiff | tree
2019-04-24 Gabe Blackpython: Make Port roles a more generic concept. commit | commitdiff | tree
2019-04-23 Ciro Santillipython: fix tracing after Python 3 refactor commit | commitdiff | tree
2019-04-22 Alexandru Dutusim-se: Enhance clone for X86KvmCPU commit | commitdiff | tree
2019-04-22 Danielmem-cache: Fix fix of replacement count commit | commitdiff | tree
2019-04-22 Gabe Blackcpu: Eliminate the ProxyThreadContext class. commit | commitdiff | tree
2019-04-22 Po-Hao Suconfigs: Use param to get number of processors commit | commitdiff | tree
2019-04-19 Daniel R. Carvalhomem-cache: Fix increasing replacement count commit | commitdiff | tree
2019-04-19 Daniel R. Carvalhomem-cache: Remove blk_addr from Queue::trySatisfyFunctional commit | commitdiff | tree
2019-04-19 Daniel R. Carvalhomem-cache: Add match functions to QueueEntry commit | commitdiff | tree
2019-04-19 Daniel R. Carvalhomem: Add packet matching functions commit | commitdiff | tree
2019-04-19 Daniel R. Carvalhomem-cache: Move Target to QueueEntry commit | commitdiff | tree
2019-04-19 Daniel R. Carvalhomem-cache: Assert Entry inherits from QueueEntry in... commit | commitdiff | tree
2019-04-19 Daniel R. Carvalhomem: Make DRAMCtrl::decodeAddr const commit | commitdiff | tree
2019-04-19 Daniel R. Carvalhomem: Allow packet to provide its own addr range commit | commitdiff | tree
2019-04-16 Andrea Mondellimem: missing override specifier commit | commitdiff | tree
2019-04-14 Gabe Blackmem: Teach SimpleMem to return a MemBackdoor when appro... commit | commitdiff | tree
2019-04-14 Gabe Blackmem: Maintain a back door into the AbstractMem's backin... commit | commitdiff | tree
2019-04-12 Rutuja Ozatests: Add tests for learning_gem5 configs commit | commitdiff | tree
2019-04-12 Jason Lowe... tests: Add protocol as an option to SconsFixture commit | commitdiff | tree
2019-04-12 Hoa Nguyentests: add riscv to cpu tests commit | commitdiff | tree
2019-04-11 Anis Peysieuxmem-cache: Fix RRPV for RRIP commit | commitdiff | tree
2019-04-11 Giacomo Travagliniarch-arm: Enable PMSELR_EL0 read in PMU commit | commitdiff | tree
2019-04-10 Gabe Blackmem: Plumb backdoor requests through the xbar classes. commit | commitdiff | tree
2019-04-10 Gabe Blacksystemc: Teach the TLM bridges how to use gem5's new... commit | commitdiff | tree
2019-04-10 Gabe Blackmem: Add sendAtomicBackdoor/recvAtomicBackdoor port... commit | commitdiff | tree
2019-04-10 Nikos Nikolerismem-cache: Fix MSHR handling of cache clean requests commit | commitdiff | tree
2019-04-10 Giacomo Travaglinicpu: O3 switchFreeList checking VecElems instead of... commit | commitdiff | tree
2019-04-08 Jason Lowe... learning_gem5,configs: Update ruby_test commit | commitdiff | tree
2019-04-08 Jason Lowe... learning_gem5: Fix vector port panic in SimpleCache commit | commitdiff | tree
2019-04-08 Jason Lowe... configs: Fix import path error in learning_gem5 part3 commit | commitdiff | tree
2019-04-08 Jason Lowe... configs: Add full path for learning_gem5 binaries commit | commitdiff | tree
2019-04-08 Ryan Gambordconfigs: Removed redudant exec-style import commit | commitdiff | tree
2019-04-06 Gabe Blackmem: Add a MemBackdoor type to track memory backdoors. commit | commitdiff | tree
2019-04-05 Nikos Nikoleriscpu: Correctly account for executed instructions in... commit | commitdiff | tree
2019-04-05 Ryan Gambordmem-cache: ambiguous use of abs function commit | commitdiff | tree
2019-04-05 Jason Lowe... mem: Reverse order of write/read mem queue check commit | commitdiff | tree
2019-04-05 Jason Lowe... tests: Add Jenkins presubmit and continuous test scripts commit | commitdiff | tree
2019-04-04 Javier Buenomem-cache: AMPM Prefetcher fails when restoring from... commit | commitdiff | tree
2019-04-03 Andrea Mondellimisc: Removed inconsistency in O3* debug msgs commit | commitdiff | tree
2019-04-03 Andrea Mondelliarch-mips: added missing override specifier (o3) commit | commitdiff | tree
2019-04-03 Javier Buenomem-cache: Fix PIF prefetcher compilation error with... commit | commitdiff | tree
2019-04-03 Javier Buenomem-cache: ISB prefetcher was triggering an assertion commit | commitdiff | tree
2019-04-03 Javier Buenomem-cache: Fix panic in Indirect Memory prefetcher commit | commitdiff | tree
2019-04-02 Giacomo Travaglinidev-arm: Make GICv3 maintenance interrupt an ArmInterrupt commit | commitdiff | tree
2019-04-02 Ivan Pizarromem-cache: Proactive Instruction Fetch Implementation commit | commitdiff | tree
2019-04-01 Andrea Mondellidev-arm: Correct cast of template parameter commit | commitdiff | tree
2019-03-29 Gabe Blacksystemc: Templatize the gem5/TLM bridge SimObjects. commit | commitdiff | tree
2019-03-29 Gabe Blacksystemc: Delete extra code from src/systemc/tlm_bridge. commit | commitdiff | tree
2019-03-29 Gabe Blacksystemc: Create unified gem5/TLM bridge SimObjects. commit | commitdiff | tree
2019-03-29 Gabe Blacktlm: Initial import of tlm/gem5 bridge code. commit | commitdiff | tree
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