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yosys.git
2021-03-08
Marcelina Kościelnicka
memory_dff: Remove code looking for $mux cells.
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2021-03-08
Marcelina Kościelnicka
tests/bram: Do not generate write address collisions.
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2021-03-07
Dan Ravensloft
Replace assert in abc9_ops with more useful error message
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2021-03-07
whitequark
Merge pull request #2626 from zachjs/param-no-default
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2021-03-07
whitequark
Merge pull request #2632 from zachjs/width-limit
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2021-03-06
Zachary Snow
sv: fix some edge cases for unbased unsized literals
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2021-03-06
Marcelina Kościelnicka
proc_clean: Fix empty case removal conditions.
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2021-03-06
Marcelina Kościelnicka
Remove a few functions that, in fact, did not exist...
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2021-03-05
Dan Ravensloft
Replace assert in addModule with more useful error...
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2021-03-05
whitequark
Merge pull request #2635 from whitequark/cxxrtl-memrd...
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2021-03-05
whitequark
Merge pull request #2634 from whitequark/cxxrtl-debug...
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2021-03-05
whitequark
Merge pull request #2633 from whitequark/cxxrtl-no-top
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2021-03-05
whitequark
cxxrtl: follow aliases to outlines when emitting $memrd...
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2021-03-05
whitequark
cxxrtl: add pass debug flag to show assigned wire types.
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2021-03-05
whitequark
cxxrtl: don't crash on empty designs.
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2021-03-04
Zachary Snow
verilog: impose limit on maximum expression width
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2021-03-04
Claire Xen
Update command-reference-manual.tex
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2021-03-04
Claire Xen
Update README
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2021-03-02
Zachary Snow
sv: support for parameters without default values
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2021-03-02
whitequark
Merge pull request #2620 from zachjs/port-int-types
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2021-03-01
Zachary Snow
verilog: fix sizing of ports with int types in module...
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2021-03-01
Marcelina Kościelnicka
Bump version
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2021-03-01
Zachary Snow
verilog: fix handling of nested ifdef directives
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2021-03-01
Zachary Snow
Set aside extraneous tests in simple_abc9 test suite
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2021-03-01
Claire Xen
Merge pull request #2523 from tomverbeure/define_synthesis
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2021-03-01
Claire Xen
Merge pull request #2524 from bkbncn/patch-1
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2021-03-01
whitequark
Merge pull request #2617 from RobertBaruch/doc
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2021-03-01
whitequark
Merge pull request #2615 from zachjs/genrtlil-conflict
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2021-03-01
whitequark
Merge pull request #2618 from zachjs/int-types
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2021-02-28
Zachary Snow
sv: extended support for integer types
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2021-02-27
Robert Baruch
RTLIL Documentation: switch in process is optional
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2021-02-27
Claire Xen
Update issue_template.md
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2021-02-26
Zachary Snow
genrtlil: improve name conflict error messaging
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2021-02-26
Michael Singer
Add tests for $countbits
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2021-02-26
Michael Singer
Implement $countones, $isunknown and $onehot{,0}
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2021-02-26
Michael Singer
Implement $countbits function
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2021-02-26
Zachary Snow
Extend simplify() recursion warning
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2021-02-25
Marcelina Kościelnicka
Bump version
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2021-02-25
whitequark
Merge pull request #2554 from hzeller/master
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2021-02-25
Marcelina Kościelnicka
btor, smt2, smv: Add a hint on how to deal with funny...
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2021-02-25
Marcelina Kościelnicka
Fix handling of unique/unique0/priority cases in the...
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2021-02-24
TimRudy
Extend "delay" expressions to handle pair and triplet...
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2021-02-24
whitequark
Merge pull request #2607 from zachjs/logger-error-atexit
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2021-02-24
Zachary Snow
Fix double-free on unmatched logger error pattern
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2021-02-24
Marcelina Kościelnicka
Add tests for some common techmap files.
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2021-02-24
Marcelina Kościelnicka
Fix syntax error in adff2dff.v
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2021-02-23
Marcelina Kościelnicka
frontend: Make helper functions for printing locations.
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2021-02-23
whitequark
Merge pull request #2594 from zachjs/func-arg-width
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2021-02-23
Robert Baruch
int -> bool
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2021-02-23
Robert Baruch
Adds is_wire to SigBit and SigChunk
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2021-02-23
William D....
machxo2: Switch to LUT4 sim model which propagates...
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2021-02-23
William D....
machxo2: Update tribuf test to reflect active-low OE.
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2021-02-23
William D....
machxo2: Add experimental status to help.
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2021-02-23
William D....
machxo2: Add DCCA and DCMA blackbox primitives.
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2021-02-23
William D....
machxo2: Fix reversed interpretation of REG_SD config...
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2021-02-23
William D....
machxo2: Tristate is active-low.
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2021-02-23
William D....
machxo2: Fix typos in FACADE_FF sim model.
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2021-02-23
William D....
machxo2: Fix naming of TRELLIS_IO ports to match PIO...
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2021-02-23
William D....
machxo2: Improve help_mode output in synth_machxo2.
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2021-02-23
William D....
machxo2: Use attrmvcp pass to move LOC and src attribut...
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2021-02-23
William D....
machxo2: Add missing OSCH oscillator primitive.
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2021-02-23
William D....
machxo2: Add believed-to-be-correct tribuf test.
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2021-02-23
William D....
machxo2: Add passing fsm, mux, and shifter tests.
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2021-02-23
William D....
machxo2: Add add_sub test. Fix tests to include FACADE_...
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2021-02-23
William D....
machxo2: Add -noiopad option to synth_machxo2.
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2021-02-23
William D....
machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE.
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2021-02-23
William D....
machxo2: Fix cells_sim typo where OFX1 was multiply...
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2021-02-23
William D....
machxo2: synth_machxo2 now maps ports to FACADE_IO.
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2021-02-23
William D....
machxo2: Add initial value for Q in FACADE_FF.
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2021-02-23
William D....
machxo2: Add FACADE_IO simulation model. More comments...
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2021-02-23
William D....
machxo2: Add FACADE_SLICE simulation model.
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2021-02-23
William D....
machxo2: Improve FACADE_FF simulation model.
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2021-02-23
William D....
machxo2: Improve LUT4 techmap. Use same output port...
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2021-02-23
William D....
machxo2: Add dffe test.
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2021-02-23
William D....
machxo2: Add dff.ys test, fix another cells_map.v typo.
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2021-02-23
William D....
machxo2: Fix more oversights in machxo2 models. logic...
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2021-02-23
William D....
machxo2: Add test/arch/machxo2 directory (test does...
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2021-02-23
William D....
machxo2: Fix typos. test/arch/run-test.sh passes.
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2021-02-23
William D....
machxo2: Create basic techlibs and synth_machxo2 pass.
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2021-02-22
Karol Gugala
frontend: json: parse negative values
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2021-02-22
Marcelina Kościelnicka
assertpmux: Fix crash on unused $pmux output.
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2021-02-21
whitequark
Merge pull request #2586 from zachjs/tern-recurse
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2021-02-21
whitequark
Merge pull request #2591 from zachjs/verilog-preproc...
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2021-02-21
Zachary Snow
verilog: fix sizing of constant args for tasks/functions
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2021-02-19
Zachary Snow
verilog: error on macro invocations with missing argume...
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2021-02-18
Yosys Bot
Bump version
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2021-02-17
Claire Xen
Merge pull request #2590 from RobertBaruch/fix_fast_sop...
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2021-02-17
Robert Baruch
Fixes command line for abc pass in -fast -sop mode
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2021-02-16
Yosys Bot
Bump version
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2021-02-15
Claire Xen
Merge pull request #2574 from dh73/master
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2021-02-13
Yosys Bot
Bump version
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2021-02-12
Zachary Snow
verilog: support recursive functions using ternary...
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2021-02-12
gatecat
Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct
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2021-02-12
Miodrag Milanovic
Ganulate Verific support
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2021-02-12
Yosys Bot
Bump version
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2021-02-11
whitequark
Merge pull request #2573 from zachjs/repeat-call
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2021-02-11
Zachary Snow
Merge pull request #2578 from zachjs/genblk-port
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2021-02-11
Zachary Snow
Merge pull request #2584 from antmicro/atom_type_signedness
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2021-02-11
Kamil Rakoczy
Add missing is_signed to type_atom
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2021-02-07
Zachary Snow
verlog: allow shadowing module ports within generate...
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