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gem5.git
2008-04-08
Ali Saidi
SCons: Make BATCH options global sticky so libelf is...
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2008-04-08
Ali Saidi
SCons: Add check for SCons version since the latest...
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2008-03-25
Ali Saidi
IGbE: Fix bug that limits wire performance a bit
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2008-03-25
Steve Reinhardt
Automated merge with ssh://daystrom.m5sim.org//repo/m5
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2008-03-25
Steve Reinhardt
Fix handling of writeback-induced writebacks in atomic...
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2008-03-25
Gabe Black
X86: Put an RTC into the CMOS part of the southbridge.
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2008-03-25
Gabe Black
Devices: Separate out the MC146818 RTC so both Alpha...
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2008-03-25
Gabe Black
X86: Turn #defines into consts.
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2008-03-25
Gabe Black
X86: Start implementing the south bridge stuff.
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2008-03-25
Gabe Black
X86: Change the Opteron platform to be the PC platform.
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2008-03-24
Steve Reinhardt
Delete the Request for a no-response Packet
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2008-03-24
Steve Reinhardt
Don't FastAlloc MSHRs since we don't allocate them...
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2008-03-24
Steve Reinhardt
Add FAST_ALLOC_DEBUG and FAST_ALLOC_STATS as SConstruct...
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2008-03-23
Steve Reinhardt
Fix cache problem with writes to tempBlock
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2008-03-20
Gabe Black
MIPS: Check endianness of binaries in SE mode.
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2008-03-18
Steve Reinhardt
Update long regression stats for semi-recent cache...
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2008-03-17
Steve Reinhardt
Fix a few Packet memory leaks.
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2008-03-17
Steve Reinhardt
Restructure bus timing calcs to cope with pkt being...
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2008-03-15
Steve Reinhardt
Fix subtle cache bug where read could return stale...
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2008-03-16
Ali Saidi
Simpoints: Fix regression bug/Don't set process.simpoin...
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2008-03-07
Gabe Black
Merge
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2008-03-07
Gabe Black
X86: Refine the local APIC.
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2008-03-06
Vilas Sridharan
O3CPU: Don't call dumpInsts if DEBUG is not defined
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2008-03-01
Gabe Black
X86: Don't map the local APIC into the physical address...
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2008-02-29
Ali Saidi
Added tag m5_2.0_beta4 for changeset cad8c2b5d2ec
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2008-02-29
Ali Saidi
Added tag m5_2.0_beta5 for changeset fb826c79a385
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2008-02-29
Lisa Hsu
Error out if -s is used without --caches (instead of...
m5_2.0_beta5
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2008-02-29
Ali Saidi
Configs: Make sure options don't conflict
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2008-02-29
Ali Saidi
Configs: Fix some bugs we introduced in the simpoints...
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2008-02-27
Steve Reinhardt
Automated merge with ssh://daystrom.m5sim.org//repo/m5
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2008-02-27
Steve Reinhardt
Update outputs for quick tests to reflect fixed cache...
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2008-02-27
Korey Sewell
Add comments in code to describe bug conditions.
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2008-02-27
Korey Sewell
Fix Load/Store Queue squashing after a SMT thread is...
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2008-02-27
Korey Sewell
Fix offset in removeThread() function so that float...
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2008-02-27
Steve Reinhardt
Revamp cache timing access mshr check to make stats...
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2008-02-27
Rick Strong
Configs: Make using Simpoints easier with some config...
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2008-02-27
Gabe Black
X86: Put in initial implementation of the local APIC.
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2008-02-27
Gabe Black
X86: Implement the INVLPG instruction and the TIA microop.
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2008-02-27
Gabe Black
TLB: Make a TLB base class and put a virtual demapPage...
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2008-02-27
Gabe Black
X86: Get PCI config space to work, and adjust address...
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2008-02-27
Steve Reinhardt
Cache: better comments particularly regarding writeback...
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2008-02-26
Ali Saidi
Update make release, README, and RELEASE_NOTES for b5
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2008-02-26
Gabe Black
Bus: Update the stats for the recent bus fix.
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2008-02-26
Gabe Black
Bus: Fix the bus timing to be more realistic.
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2008-02-22
Vilas Sridharan
add instruction count fast forwaing and max instruction...
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2008-02-19
Stephen Hines
Added ARM_SE as a build option.
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2008-02-16
Steve Reinhardt
Update stats for new writeback behavior.
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2008-02-16
Steve Reinhardt
Make L2+ caches allocate new block for writeback misses
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2008-02-16
Steve Reinhardt
Update stats for some unknown minor x86 changes
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2008-02-14
Ali Saidi
CPU: move the PC Events code to a place where the code...
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2008-02-14
Ali Saidi
Configs: Change Simulation.py to return a subclass...
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2008-02-11
Ali Saidi
Update copyright dates
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2008-02-11
Steve Reinhardt
Automated merge with file:/home/stever/hg/m5-orig
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2008-02-11
Steve Reinhardt
EXTRAS now points to src instead of needing 'src' subdir.
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2008-02-11
Steve Reinhardt
Wait to set BUILD_DIR until *after* env is copied.
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2008-02-11
Nicolas Zea
Bus: Only update port cache when there is an item to...
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2008-02-11
Ali Saidi
IGbE: Fix a couple of bugs.
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2008-02-10
Steve Reinhardt
Fix #include lines for renamed cache files.
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2008-02-10
Steve Reinhardt
Rename cache files for brevity and consistency with...
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2008-02-06
Stephen Hines
Make the Event::description() a const function
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2008-02-06
Stephen Hines
Add base ARM code to M5
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2008-02-06
Steve Reinhardt
Cleaned up os.path imports a bit.
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2008-02-06
Steve Reinhardt
Make EXTRAS work for SConsopts too.
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2008-01-23
Gabe Black
X86: Put an SMBios/DMI table in memory.
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2008-01-23
Gabe Black
X86: Optomize the bit scanning instruction microassembl...
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2008-01-22
Gabe Black
X86: Implement and attach the BSR and BSF instructions.
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2008-01-21
Gabe Black
X86: Fill out group17 in the decoder.
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2008-01-21
Gabe Black
X86: Use the existing boot_osflags instead of duplicati...
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2008-01-16
Ali Saidi
Update long o3 regressions for o3 change in previous...
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2008-01-15
Steve Reinhardt
Update O3 ref outputs: very minor stats change due...
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2008-01-14
Ke Meng
The reason is that the event is supposed to put the...
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2008-01-12
Gabe Black
X86: Redo the bit test instructions.
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2008-01-12
Gabe Black
X86: Fix the wrmsr instruction.
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2008-01-12
Gabe Black
X86: Make the effective segment base shadow the regular...
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2008-01-12
Gabe Black
X86: Make the IO ports work using extra physical addres...
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2008-01-12
Gabe Black
X86: Fix the general IO instructions dataSize.
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2008-01-06
Geoffrey Blake
Temporary fix for ll/sc bug see flyspray task for more...
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2008-01-02
Steve Reinhardt
Very minor memtest regression stats changes from recent...
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2008-01-02
Steve Reinhardt
Add ReadRespWithInvalidate to handle multi-level cohere...
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2008-01-02
Steve Reinhardt
Mark cache-to-cache MSHRs as downstreamPending when...
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2008-01-02
Steve Reinhardt
Don't DPRINTF in the middle of a PrintReq.
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2008-01-02
Steve Reinhardt
Bug fix: functional cache port now needs otherPort...
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2008-01-02
Steve Reinhardt
Additional comments and helper functions for PrintReq.
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2008-01-02
Steve Reinhardt
Add functional PrintReq command for memory-system debug...
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2008-01-02
Steve Reinhardt
Fix formatting and comments in cache_impl.hh
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2008-01-01
Gabe Black
SPARC: Fix a bug where the TLB would match against...
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2007-12-18
Ali Saidi
Checkpointing: Fix a bug in the simulation script when...
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2007-12-16
Ali Saidi
CPU: Update where the simple cpus read their cpu id...
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2007-12-11
Steve Reinhardt
Fix minor bug in util/style.py
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2007-12-03
Gabe Black
X86: Update the parser reference output which has myste...
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2007-12-03
Gabe Black
X86: Please excuse my dear Aunt Sally. (precedence...
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2007-12-02
Gabe Black
X86: Make sure the memory index is calculated using...
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2007-12-02
Gabe Black
X86: Fix a copy/paste mistake where the bit test instru...
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2007-12-02
Gabe Black
X86: Make the page not present panic more descriptive.
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2007-12-02
Gabe Black
X86: Start setting up the real mode data structure.
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2007-12-02
Gabe Black
X86: Make the 0xA0-0xA3 versions of mov use the right...
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2007-12-02
Gabe Black
X86: Add in a missing "break".
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2007-12-02
Gabe Black
X86: Actually do something for the MiscRegFile clear...
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2007-12-02
Gabe Black
X86: Move startup code to the system object to initiali...
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2007-12-02
Gabe Black
X86: Add a missing microcode file to the sconscript.
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