yosys.git
2022-02-04 Miodrag MilanovicError detection for co-simulation
2022-02-04 Miodrag Milanovicbug fix and cleanups
2022-02-02 Miodrag MilanovicAdd test cases for co-simulation
2022-02-02 Miodrag MilanovicFix Visual Studio build
2022-02-02 Miodrag Milanovicrespect hide_internal flag
2022-02-02 Miodrag Milanovicunify cycles counting and cleanup
2022-02-02 Miodrag Milanovicadded stimulus mode and param check
2022-01-31 Miodrag Milanovicerror when no signal found
2022-01-31 Miodrag MilanovicCleanup
2022-01-31 Miodrag MilanovicCompare bits when not all are defined
2022-01-31 Miodrag MilanovicCleanup
2022-01-31 Miodrag Milanovicmessage update
2022-01-31 Miodrag MilanovicDisplay simulation time data
2022-01-31 Miodrag MilanovicUse edges when explicit
2022-01-31 Miodrag MilanovicUpdating initial state and checks
2022-01-31 Miodrag MilanovicFix scope
2022-01-28 Miodrag Milanoviccheck if stop before start
2022-01-28 Miodrag Milanovicset initial state, only flip-flops
2022-01-28 Miodrag Milanovicignore not found private signals
2022-01-28 Miodrag Milanovicpreserve VCD mangled names
2022-01-28 Miodrag Milanovicdetect edges even when x
2022-01-28 Miodrag Milanovicrecursive check
2022-01-28 Miodrag Milanoviccleanup
2022-01-28 Miodrag MilanovicDo actual compare
2022-01-28 Miodrag MilanovicFix for limit_range_end when not writing vcd
2022-01-28 Miodrag MilanovicAdd more options and time handling
2022-01-26 Miodrag Milanovicupdate version
2022-01-26 Miodrag MilanovicDisplay values of outputs
2022-01-26 Miodrag MilanovicFix tabs/spaces
2022-01-26 Miodrag MilanovicCheck if stimulated
2022-01-26 Miodrag MilanovicRead fst and use data to set inputs
2022-01-26 Miodrag MilanovicAdd fstdata helper class
2022-01-26 Miodrag MilanovicCleanup of config to support platforms
2022-01-26 Miodrag MilanovicAdd ability to write to FST file
2022-01-25 Miodrag MilanovicAdd FST library
2022-01-20 github-actions... Bump version
2022-01-19 gatecatnexus: Fix BB sim model
2022-01-19 Miodrag MilanovicRemoved dbits 8 since 9 will always be picked
2022-01-19 Miodrag MilanovićMerge pull request #3120 from Icenowy/anlogic-bram
2022-01-18 github-actions... Bump version
2022-01-17 Miodrag MilanovićMerge pull request #3162 from YosysHQ/mmicko/windows_gu...
2022-01-17 Miodrag MilanovićUpdate guidelines/Windows
2022-01-17 N. EngelhardtMerge pull request #3145 from nakengelhardt/advertise_s...
2022-01-17 N. Engelhardtmention distributions' package manager
2022-01-17 Miodrag MilanovićAdd info about VS build
2022-01-12 github-actions... Bump version
2022-01-11 Miodrag MilanovicForgot one
2022-01-11 Miodrag MilanovicChange url to https
2022-01-11 Miodrag MilanovicNext dev cycle
2022-01-11 Miodrag MilanovicRelease version 0.13 yosys-0.13
2022-01-11 Miodrag MilanovicUpdate CHANGELOG
2022-01-09 github-actions... Bump version
2022-01-08 Zachary Snowsv: auto add nosync to certain always_comb local vars
2022-01-08 Zachary Snowsv: fix size cast internal expression extension
2022-01-05 github-actions... Bump version
2022-01-04 Zachary Snowlogger: fix unmatched expected warnings and errors
2022-01-04 Austin Seippopt_dff: fix sequence point copy paste bug
2022-01-04 N. Engelhardtmention tabby+oss cad suite in readme
2022-01-04 gatecatmanual: Fix cell-stmt order
2022-01-04 github-actions... Bump version
2022-01-03 Zachary Snowfix iverilog compatibility for new case expr tests
2022-01-03 Zachary Snowfixup verilog doubleslash test
2022-01-03 Zachary Snowsv: fix size cast clipping expression width
2022-01-03 Miodrag MilanovicUpdate manual
2021-12-26 github-actions... Bump version
2021-12-25 CatherineMerge pull request #3127 from whitequark/cxxrtl-no...
2021-12-25 Catherinecxxrtl: don't reset elided wires with \init attribute.
2021-12-22 github-actions... Bump version
2021-12-21 Loftyintel_alm: disable 256x40 M10K mode
2021-12-21 github-actions... Bump version
2021-12-20 Marcelina Kościelnickamemory_share: Fix SAT-based sharing for wide ports.
2021-12-19 github-actions... Bump version
2021-12-18 Zachary Snowfix width detection of array querying function in case...
2021-12-17 Icenowy Zhenganlogic: support BRAM mapping
2021-12-17 github-actions... Bump version
2021-12-16 CatherineMerge pull request #3115 from whitequark/issue-3112
2021-12-16 CatherineMerge pull request #3114 from whitequark/issue-3113
2021-12-16 Thomas Sailerpreprocessor: do not destroy double slash escaped ident...
2021-12-15 Catherinecxxrtl: demote wires not inlinable only in debug_eval...
2021-12-15 Catherinebugpoint: avoid infinite loop between -connections...
2021-12-15 github-actions... Bump version
2021-12-14 CatherineMerge pull request #3111 from whitequark/issue-3110
2021-12-14 Claire Xenia... Hotfix for run_shell auto-detection
2021-12-14 CatherineFix null pointer dereference after failing to extract...
2021-12-14 github-actions... Bump version
2021-12-13 Claire XenMerge pull request #3108 from YosysHQ/claire/verificdefs
2021-12-13 Claire Xenia... Add YOSYS to the implicitly defined verilog macros...
2021-12-13 github-actions... Bump version
2021-12-12 Marcelina KościelnickaAdd clean_zerowidth pass, use it for Verilog output.
2021-12-12 CatherineMerge pull request #3105 from whitequark/cxxrtl-reset...
2021-12-12 github-actions... Bump version
2021-12-12 Marcelina KościelnickaFix unused param warning with ENABLE_NDEBUG.
2021-12-12 Marcelina Kościelnickartlil: Dump empty connections when whole module is...
2021-12-11 Catherinecxxrtl: preserve interior memory pointers across reset.
2021-12-11 CatherineMerge pull request #3103 from whitequark/write_verilog...
2021-12-11 whitequarkcxxrtl: use unique_ptr<value<>[]> to store memory contents.
2021-12-11 whitequarkwrite_verilog: dump zero width sigspecs correctly.
2021-12-11 github-actions... Bump version
2021-12-10 Miodrag MilanovićMerge pull request #3102 from YosysHQ/claire/enumxz
2021-12-10 Claire Xenia... Fix verific import of enum values with x and/or z
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